NT512D72S4PB0FU-6K datasheet, PDF

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NT512D72S4PB0FU-6K: DescriptionDDR DRAM Module, 64MX72, 0.7ns, CMOS, DIMM-184; Categorystorage storage; File Size289KB，20 Pages; ManufacturerNanya; Websitehttp://www.nanya.com/cn; Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.

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NT512D72S4PB0FU-6K Overview

DDR DRAM Module, 64MX72, 0.7ns, CMOS, DIMM-184

NT512D72S4PB0FU-6K Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Nanya
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
JESD-609 code	e4
memory density	4831838208 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.36 A
Maximum slew rate	5.85 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

NT512D72S4PB0FU-6K Preview

NT512D72S4PB0FU / NT512D72S4PB0GU

NT256D72S89B0FU / NT256D72S89B0GU

512MB and 256MB

PC2700 and PC2100

Registered DDR DIMM

184 pin Registered DDR DIMM

Based on DDR333/266 256M bit B Die device

Features

• 184 Dual In-Line Registered Memory Module (RDIMM)

• Registered DDR DIMM based on 256M bit die B device,

organized as either 32Mbx8 or 64Mbx4

• Performance:

PC2700 PC2100

Speed Sort

DIMM

CAS

Latency

Clock Frequency

Clock Cycle

2.5

166

333

75B

2.5

133

7.5

266

MHz

Unit

• Differential clock inputs

• Data is read or written on both clock edges

• DRAM DLL aligns DQ and DQS transitions with clock transitions

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM

CAS

Latency: 2.5, 2

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 7.8

µs

Max. Average Periodic Refresh Interval

• Serial Presence Detect EEPROM

• Gold contacts

• SDRAMs are packaged in CSP or TSOP packages

DQ Burst Frequency

• Intended for 133 and 166 MHz applications

• Inputs and outputs are SSTL-2 compatible

• Error Check Correction (ECC) support

• Phase lock loop (PLL) clock driver to reducing clock loading

• Registered inputs with one clock delay

• V

= V

DDQ

= 2.5V ± 0.2V

• SDRAMs have 4 internal banks for concurrent operation

Description

NT512D72S4PB0FU, NT512D72S4PB0GU, NT256D72S89B0FU and NT256D72S89B0GU are registered 184-Pin Double Data Rate

(DDR) Synchronous DRAM Dual In-Line Memory Modules (DIMM). NT512D72S4PB0FU are 512MB modules with ECC organized as

single rank using eighteen 64Mbx4 CSP devices. NT512D72S4PB0FU are 512MB modules with ECC organized as single rank using

eighteen 64Mbx4 TSOP devices. NT256D72S89B0FU are 256MB modules with ECC organized as a single rank using nine 32Mbx8 CSP

devices. NT256D72S89B0GU are 256MB modules with ECC organized as a single rank using nine 32Mbx8 TSOP devices.

Depending on the speed grade, these DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves

high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device

CAS

latency and burst type/ length/operation

type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be

accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC and the remaining are

available for use by the customer.

REV 2.1

Mar 22, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D72S4PB0FU / NT512D72S4PB0GU

NT256D72S89B0FU / NT256D72S89B0GU

Registered DDR DIMM

Ordering Information

Part Number

NT512D72S4PB0FU-6K

NT256D72S89B0FU-6K

Organization

64Mx72

DDR333

32Mx72

64Mx72

DDR266B

NT256D72S89B0GU-75B

32Mx72

2.5-3-3 100MHz (10ns @ CL = 2)

2.5-3-3 133MHz (7.5ns @ CL = 2)

2.5V

NT512D72S4PB0GU-75B

PC2100 133MHz (7.5ns @ CL = 2.5)

Gold

Speed

Power

Leads

PC2700 166MHz (6ns @ CL = 2.5)

Note: The registered inputs will add 1 initial clock delay to all modules

For the closest sales office or information, please visit:

www.nanya.com

Nanya Technology Corporation

Hwa Ya Technology Park 669

Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

REV 2.1

Mar 22, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D72S4PB0FU / NT512D72S4PB0GU

NT256D72S89B0FU / NT256D72S89B0GU

Registered DDR DIMM

Pin Description

CK0, CK1, CK2,

CK0, CK1, CK2

CKE0, CKE1

RAS

CAS

S0, S1

A0-A9, A11, A12

A10/AP

BA0, BA1

REF

DDID

Differential Clock Inputs.

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

Chip Selects

Address Inputs

Address Input/Auto-precharge

SDRAM Bank Address Inputs

Ref. Voltage for SSTL_2 inputs

Identification flag.

DQ0-DQ63

DQS0-DQS7

DM0-DM7

DDQ

SCL

SDA

SA0-2

DDSPD

Data input/output

Bidirectional data strobes

Input Data Mask

Power

Supply voltage for DQs

Ground

No Connect

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address Inputs

Serial EEPROM positive power supply

Pinout

Front

REF

DQ0

DQ1

DQS0

DQ2

DQ3

DQ8

DQ9

DQS1

DDQ

CK1

DQ10

DQ11

CKE0

DDQ

DQ16

DQ17

DQS2

DQ18

DDQ

DQ19

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

DQ4

DQ5

DDQ

DM0/DQS9

DQ6

DQ7

DDQ

DQ12

DQ13

DM1/DQS10

DQ14

DQ15

CKE1

DDQ

DQ20

A12

DQ21

A11

DM2/DQS11

DQ22

DQ23

KEY

DQ32

DDQ

DQ33

DQS4

DQ34

BA0

DQ35

DQ40

Front

DQ24

DQ25

DQS3

DQ26

DQ27

BA1

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

KEY

145

146

147

148

149

150

151

152

153

DQ36

DQ37

DM4/DQS13

DQ38

DQ39

DQ44

Back

DQ28

DQ29

DDQ

DM3/DQS12

DQ30

DQ31

DDQ

CK0

A10

DDQ

Front

DDQ

DQ41

CAS

DQS5

DQ42

DQ43

DQ48

DQ49

CK2

DDQ

DQS6

DQ50

DQ51

DDID

DQ56

DQ57

DQS7

DQ58

DQ59

SDA

SCL

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

DDQ

DM5/DQS14

DQ46

DQ47

DDQ

DQ52

DQ53

DM6/DQS15

DQ54

DQ55

DDQ

DQ60

DQ61

DM7/DQS16

DQ62

DQ63

DDQ

SA0

SA1

SA2

DDSPD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

REV 2.1

Mar 22, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D72S4PB0FU / NT512D72S4PB0GU

NT256D72S89B0FU / NT256D72S89B0GU

Registered DDR DIMM

Input/Output Functional Description

Symbol

CK0, CK1, CK2,

CK0, CK1, CK2

CKE0, CKE1

(SSTL)

Type

Polarity

Cross

point

Active

High

Function

The system clock inputs. All address and command lines are sampled on the cross point of

the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is synchronized to the input

clock.

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

Enables the associated DDR SDRAM command decoder when low and disables the

S0, S1

(SSTL)

Active

Low

Active

Low

command decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is

selected by S1.

RAS, CAS, WE

REF

DDQ

BA0, BA1

(SSTL)

Supply

(SSTL)

When sampled at the positive rising edge of the clock,

RAS, CAS, WE

define the operation to

be executed by the SDRAM.

Reference voltage for SSTL-2 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when

sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

A0 - A9

A10/AP

A11, A12

(SSTL)

invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,

auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,

auto-precharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63

DQS0 - DQS7,

DQS9 – DQS16

CB0 – CB7

DM0 – DM8

, V

SA0 – SA2

SDA

SCL

DDSPD

Supply

(SSTL)

Input

Supply

Active

High

Active

High

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write operation if it is high.

In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is

not used on x64 modules.

Power and ground for the DDR SDRAM input buffers and core logic

Address inputs. Connected to either V

or V

on the system board to configure the Serial

Presence Detect EEPROM address.

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pull-up.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

Serial EEPROM positive power supply.

(SSTL)

REV 2.1

Mar 22, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D72S4PB0FU / NT512D72S4PB0GU

NT256D72S89B0FU / NT256D72S89B0GU

Registered DDR DIMM

Functional Block Diagram

1 Rank, 18 devices, 64Mbx4 DDR SDRAMs

RS0

DQS0

DQ0

DQ1

DQ2

DQ3

DM0/DQS9

DQ4

DQ5

DQ6

DQ7

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS8

BA0-

BA1

A0-A12

RBA0-

RBA1

RA0-RA12

CKE

RCKE0

Notes :

REV 2.1

Mar 22, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

0KC

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/CS relationships are maintained as shown.

3. DQ/DQS resistors are 22 Ohms.

4. V

DDID

strap connections (for memory device V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

5. Address and control resistors are 22 Ohms.

TESER

S AC

SAR

S ACR

S A RR

EW R

0SR

: SDRAMs D0-D17

BA0-BA1 : SDRAMs D0-D17

A0-A12 : SDRAMs D0-D17

: SDRAMs D0-D17

CKE : SDRAMs D0-D17

: SDRAMs D0-D17

DDSPD

DDQ

REF

DDID

Serial PD

--------- PLL*

CK0,

* Wire per Clock Loading Table/Wiring Diagrams

I/O 0

I/O 1

I/O 2

I/O 3

DM8/DQS17

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM7/DQS16

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM6/DQS15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM5/DQS14

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM4/DQS13

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM3/DQS12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM2/DQS11

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DM1/DQS10

I/O 0

I/O 1

I/O 2

I/O 3

D10

D11

D12

D13

D14

D15

D16

D17

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

Serial PD

D0-D17

Strap : see Note 4

S AC

SA R

KCP

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