NT5TU32M16BG-25D datasheet, PDF

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NT5TU32M16BG-25D: DescriptionDDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 0.80 MM PITCH, GREEN, BGA-84; Categorystorage storage; File Size2MB，80 Pages; ManufacturerNanya; Websitehttp://www.nanya.com/cn; Environmental Compliance; Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.

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NT5TU32M16BG-25D Overview

DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 0.80 MM PITCH, GREEN, BGA-84

NT5TU32M16BG-25D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nanya
Parts packaging code	BGA
package instruction	TFBGA, BGA84,9X15,32
Contacts	84
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	400 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B84
length	12.5 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	84
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA84,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum standby current	0.007 A
Maximum slew rate	0.27 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

NT5TU32M16BG-25D Preview

NT5TU128M4BE

NT5TU64M8BE

NT5TU32M16BG

512Mb DDR2 SDRAM B-Die

Features

• 1.8V ± 0.1V Power Supply Voltage

• 4 internal memory banks

• Programmable CAS Latency: 3, 4, 5, and 6

• Programmable Additive Latency: 0, 1, 2, 3, and 4

• Write Latency = Read Latency -1

• Programmable Burst Length: 4 and 8

• Programmable Sequential / Interleave Burst

• OCD (Off-Chip Driver Impedance Adjustment)

• ODT (On-Die Termination)

• 4 bit prefetch architecture

• 1k page size for x 4 & x 8,

2k page size for x16

• Data-Strobes: Bidirectional, Differential

• Strong and Weak Strength Data-Output Driver

• Auto-Refresh and Self-Refresh

• Power Saving Power-Down modes

• 7.8 µs max. Average Periodic Refresh Interval

• Packages:

60 Ball BGA for x4/x8 components

84 Ball BGA for x16 component

• RoHS Compliance

Description

The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a high-

speed CMOS Double Data Rate 2 SDRAM containing

536,870,912 bits. It is internally configured as a quad-bank

DRAM.

The 512Mb chip is organized as either 32Mbit x 4 I/O x 4

bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank

device. These synchronous devices achieve high speed dou-

ble-data-rate transfer rates of up to 533 Mb/sec/pin for gen-

eral applications.

The chip is designed to comply with all key DDR2 DRAM key

features: (1) posted CAS with additive latency, (2) write

latency = read latency -1, (3) normal and weak strength data-

output driver, (4) variable data-output impedance adjustment

and (5) an ODT (On-Die Termination) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS pair in a source synchronous fash-

ion. A 14 bit address bus for x4 and x8 organised compo-

nents and a 13 bit address bus for x16 components is used to

convey row, column, and bank address devices.

These devices operate with a single 1.8V+/-0.1V power sup-

ply and are available in BGA packages.

An Auto-Refresh and Self-Refresh mode is provided along

with various power-saving power-down modes.

REV 1.5

06/2008

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5TU128M4BE

NT5TU64M8BE

NT5TU32M16BG

512Mb DDR2 SDRAM B-Die

Pin Configuration - 60 balls 0.8mmx0.8mm Pitch BGA Package (x4/x8)

See the balls through the package.

VDD

VDDQ

VDDL

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10/AP

VSS

VDD

A12

VSS

VDDQ

DQ3

VSS

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

DQS

VSSQ

DQ0

VSSQ

A13

VSS

VDD

VDDQ

VDD

ODT

VDD

DQ6

VDDQ

DQ4

VDDL

NU,/RDQS

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10/AP

VSS

VDD

A12

VSS

DM/RDQS

VDDQ

DQ3

VSS

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

DQS

VSSQ

DQ0

VSSQ

A13

VSS

VDD

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

REV 1.5

06/2008

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5TU128M4BE

NT5TU64M8BE

NT5TU32M16BG

512Mb DDR2 SDRAM B-Die

Pin Configuration - 84 balls 0.8mmx0.8mm Pitch BGA Package (x16)

See the balls through the package.

x 16

VDD

DQ14

VDDQ

DQ12

VDD

DQ6

VDDQ

DQ4

VDDL

VSSQ

DQ9

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10/AP

VSS

VDD

A12

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

BA1

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS

CAS

A11

UDQS

VSSQ

DQ8

VSSQ

LDQS

VSSQ

DQ0

VSSQ

VSS

VDD

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

REV 1.5

06/2008

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5TU128M4BE

NT5TU64M8BE

NT5TU32M16BG

512Mb DDR2 SDRAM B-Die

Input/Output Functional Description

Symbol

CK, CK

Type

Input

Function

Clock:

CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-

enced to the crossings of CK and CK (both directions of crossing).

Clock Enable:

CKE high activates and CKE low deactivates internal clock signals and device

input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-

Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-

chronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-

Refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE

are disabled during Self-Refresh.

Chip Select:

All command are masked when CS is registered high. CS provides for external rank

selection on systems with multiple memory ranks. CS is considered part of the command code.

Command Inputs:

RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask:

DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Write access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM

and UDM are the input mask signals for x16 components and control the lower or upper bytes. For

x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1)

command.

Bank Address Inputs:

BA0 and BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. BA0 and BA1 also determines if the mode register or extended mode

Address Inputs:

Provides the row address for Activate commands and the column address and

Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory

array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine

whether the Precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is

to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-

code during Mode Register Set commands.

Row address A13 is used on x4 and x8 components only.

Data Inputs/Output:

Bi-directional data bus.

Data Strobe:

output with read data, input with write data. Edge aligned with read data, centered

with write data. For the x16, LDQS corresponds to the data on LDQ0 - LDQ7; UDQS corresponds

to the data on UDQ0-UDQ7. The data strobes DQS, LDQS, UDQS may be used in single ended

mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differen-

tial pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or

disables the complementary data strobe signals.

Read Data Strobe:

For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1)

for read timing. RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are

edge-aligned with read data. If RDQS, RDQS is enabled, the DM function is disabled on x8 com-

ponents.

On Die Termination:

ODT (registered HIGH) enables termination resistance internal to the DDR2

SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ,

DQS, DQS, RDQS, RDQS and DM for x8 configurations. For x16 configuration ODT is applied to

each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the

EMRS(1) is programmed to disable ODT.

No Connect:

No internal electrical connection is present.

Supply

DQ Power Supply:

1.8V +/- 0.1V

DQ Ground

DLL Power Supply:

1.8V +/- 0.1V

DLL Ground

Power Supply:

1.8V +/- 0.1V

Ground

SSTL_1.8 reference voltage

CKE

Input

RAS, CAS, WE

Input

DM, LDM, UDM

Input

BA0, BA1

Input

A0 - A13

Input

DQS, (DQS)

LDQS, (LDQS),

UDQS,(UDQS)

Input/Output

RDQS, (RDQS)

Input/Output

ODT

Input

DDQ

SSQ

DDL

SSDL

REF

REV 1.5

06/2008

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5TU128M4BE

NT5TU64M8BE

NT5TU32M16BG

512Mb DDR2 SDRAM B-Die

Ordering Information

Green

Org.

Part Number

NT5TU128M4BE-5A

NT5TU128M4BE-37B

128M x 4

NT5TU128M4BE-3C

NT5TU128M4BE-25C

NT5TU128M4BE-25D

NT5TU64M8BE-5A

NT5TU64M8BE-37B

64M x 8

NT5TU64M8BE-3C

NT5TU64M8BE-25C

NT5TU64M8BE-25D

NT5TU32M16BG-5A

32M x 16

NT5TU32M16BG-37B

NT5TU32M16BG-3C

NT5TU32M16BG-25D

Note:

84ball BGA

0.8mmx0.8mm

Pitch

60ball BGA

0.8mmx0.8mm

Pitch

60ball BGA

0.8mmx0.8mm

Pitch

Package

Speed

Clock (MHz)

200

266

333

400

200

266

333

400

200

266

333

400

CL-t

RCD

-t

3-3-3

4-4-4

5-5-5

6-6-6

3-3-3

4-4-4

5-5-5

6-6-6

3-3-3

4-4-4

5-5-5

6-6-6

REV 1.5

06/2008

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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