Field Programmable Gate Array, 96 CLBs, 1000 Gates, 225.6MHz, 96-Cell, CMOS, CPGA69, CAVITY DOWN, CERAMIC, PGA-69
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Cypress Semiconductor |
Parts packaging code | PGA |
package instruction | CAVITY DOWN, CERAMIC, PGA-69 |
Contacts | 69 |
Reach Compliance Code | not_compliant |
Other features | MAX. 56 I/OS; OTP BASED |
maximum clock frequency | 225.6 MHz |
Combined latency of CLB-Max | 6.864 ns |
JESD-30 code | S-CPGA-P69 |
JESD-609 code | e0 |
length | 29.464 mm |
Configurable number of logic blocks | 96 |
Equivalent number of gates | 1000 |
Number of entries | 64 |
Number of logical units | 96 |
Output times | 56 |
Number of terminals | 69 |
Maximum operating temperature | 85 °C |
Minimum operating temperature | -40 °C |
organize | 96 CLBS, 1000 GATES |
Package body material | CERAMIC, METAL-SEALED COFIRED |
encapsulated code | PGA |
Encapsulate equivalent code | PGA68,11X11 |
Package shape | SQUARE |
Package form | GRID ARRAY |
Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
power supply | 5 V |
Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
Certification status | Not Qualified |
Maximum seat height | 5.207 mm |
Maximum supply voltage | 5.5 V |
Minimum supply voltage | 4.5 V |
Nominal supply voltage | 5 V |
surface mount | NO |
technology | CMOS |
Temperature level | INDUSTRIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | PIN/PEG |
Terminal pitch | 2.54 mm |
Terminal location | PERPENDICULAR |
Maximum time at peak reflow temperature | NOT SPECIFIED |
width | 29.464 mm |