NT1GT72U89D2BD-3C datasheet, PDF

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NT1GT72U89D2BD-3C: DescriptionDDR DRAM Module, 128MX72, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size570KB，28 Pages; ManufacturerNanya; Websitehttp://www.nanya.com/cn; Environmental Compliance; Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.

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NT1GT72U89D2BD-3C Overview

DDR DRAM Module, 128MX72, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240

NT1GT72U89D2BD-3C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nanya
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.45 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	333 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
JESD-609 code	e4
memory density	9663676416 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum slew rate	2.35 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C

NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C

240pin DDR2 SDRAM Fully Buffered DIMM

Based on 128Mx8 (1GB/2GB/4GB), 256Mx4 (4GB), and 512Mx4 (8GB) DDR2 SDRAM

Features

•Performance:

Speed Sort

DIMM CAS Latency

fck – Clock Freqency

tck – Clock Cycle

fDQ – DQ Burst Freqency

PC2-5300

-3C

333

667

PC2-6400

-AC

400

2.5

800

Unit

MHz

Mbps

• Support SMBus protocol interface for access to the AMB

configuration registers.

• Detects errors on the channel and reports them to the host

memory controller.

• Automatic DDR2 DRAM Bus Calibration.

• Full Host Control of the DDR2 DRAMs.

• Over-Temperature Detection and Alert.

• MBIST & IBIST Test Functions.

• Transparent Mode for DRAM Test Support.

• Serial Presence Detect (SPD)

• Gold contacts

• RoHS Compliant products

• SDRAMs in 60-ball BGA Package

• 1GB/2GB: 128Mx72/256Mx72 DDR2 Fully Buffered DIMM

based on 128Mx8 DDR2 SDRAM (NT5TU128M8DE-3C/-AC)

• 4GB: 512Mx72 DDR2 Fully Buffered DIMM based on

128Mx8/256Mx4 DDR2 SDRAM (NT5TU256M4DE-3C/-AC)/

(NT5TU128M8DE-3C/-AC)

• 8GB: 1Gx72 DDR2 Fully Buffered DIMM based on 512Mx4

DDR2 SDRAM (NT5TU512T4DY-3C)

• JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line

Memory Module.

• Intended for 333MHz/400MHz applications.

• Inputs and outputs are SSTL-18 compatible.

• V

= 1.8V ± 0.1V, V

DDQ

= 1.8V ± 0.1V.

• Host Interface and AMB component industry standard

compliant.

Description

Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as an eight

bank 128Mx72 (1GB), 256Mx72 (2GB), 512Mx72 (4GB), or 1Gx72 (8GB) high-speed memory array. The module uses nine 128Mx8

(1GB), eighteen 128Mx8 (2GB), thirty-six 128Mx8/256Mx4 (4GB), or thirty-six 512Mx4 (8GB) DDR2 SDRAMs in BGA packages. These

DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files

minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface

in a 5.25” long space-saving footprint.

The DIMM is intended for use in applications operating up to 333MHz/400 MHz clock speeds and achieves high-speed data transfer

rates of up to 667 Mbps/800 Mbps. Prior to any access operation, the device

latency and burst type/length/operation type must be

programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle.

REV 1.3

03/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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