EPF10K50EFC484-1N datasheet, PDF

EPF10K50EFC484-1N: DescriptionLoadable PLD, 0.5ns, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484; CategoryProgrammable logic devices Programmable logic; File Size2MB，110 Pages; ManufacturerAltera (Intel); Environmental Compliance

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EPF10K50EFC484-1N Overview

Loadable PLD, 0.5ns, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	BGA,
Contacts	484
Reach Compliance Code	compliant
Other features	2880 LOGIC ELEMENTS
maximum clock frequency	140 MHz
JESD-30 code	S-PBGA-B484
JESD-609 code	e1
length	23 mm
Number of I/O lines	254
Number of terminals	484
Maximum operating temperature	70 °C
Minimum operating temperature
organize	254 I/O
Output function	MIXED
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
Programmable logic type	LOADABLE PLD
propagation delay	0.5 ns
Certification status	Not Qualified
Maximum seat height	2.1 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	23 mm

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