CH7010B-T datasheet, PDF - EEWORLD Datasheet

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CH7010B-T: DescriptionColor Signal Encoder, CMOS, PQFP64, 10 X 10 MM, MS-026D, LQFP-64; CategoryOther integrated circuit (IC) Consumption circuit; File Size1MB，54 Pages; ManufacturerCHRONTEL; Websitehttp://www.chrontel.com.cn/; Quintiles Integrated Circuit (Shanghai) Co., Ltd. is a wholly-owned subsidiary of Chrontel, Inc. in Shanghai. Founded in 1986, Chrontel is a company engaged in the research and development and production of mixed-signal integrated circuits. Headquartered in San Jose, Silicon Valley, USA, Chrontel has many subsidiaries and offices around the world. Our products include TV decoders, TV encoders, DVI/LVDS/HDMI encoders, digital TV demodulators, image and audio processing, display controllers and other digital-analog hybrid chips. Our products are used by many well-known OEM manufacturers such as DELL, HP, SONY, TOSHIBA, FUJITSU, etc., and we have cooperated with well-known manufacturers such as Intel for many years.

Quintiles Integrated Circuit (Shanghai) Co., Ltd. was established in 2003 and is located in Zhangjiang Hi-Tech Development Zone, Pudong. Our business includes the research, development, design, testing, production of integrated circuits and the research, design, development, production of related software; the design, debugging and maintenance of system integration; and the provision of related technical consulting and technical maintenance. We have a team of highly qualified and educated employees and enjoy comprehensive technical support from the head office. We hope that more people of insight will join us to jointly build a successful integrated circuit company.

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CH7010B-T Overview

Color Signal Encoder, CMOS, PQFP64, 10 X 10 MM, MS-026D, LQFP-64

CH7010B-T Parametric

Parameter Name	Attribute value
Maker	CHRONTEL
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	64
Reach Compliance Code	unknown
ECCN code	EAR99
Commercial integrated circuit types	COLOR SIGNAL ENCODER
input type	RGB; R-Y; B-Y; Y
JESD-30 code	S-PQFP-G64
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.1 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
video standards	PAL; NTSC

CH7010B-T Preview

CH7010B

Chrontel

CHRONTEL

CH7010 DVI / TV Output Device

1. F

EATURES

•

DVI Transmitter up to 165M pixels/second

DVI low jitter PLL

DVI hot plug detection

TV output supporting graphics resolutions up to

1024 x768 pixels

Programmable digital interface supports RGB and

YCrCb

True scale rendering engine supports underscan in all TV

output resolutions

Enhanced text sharpness and adaptive flicker removal

with up to 7 lines of filtering

Support for all NTSC and PAL formats

Provides CVBS, S-Video and SCART (RGB) outputs

TV connection detection

Programmable power management

10-bit video DAC outputs

Fully programmable through serial port

Complete Windows and DOS driver support

Low voltage interface support to graphics device

Offered in a 64-pin LQFP package

2. G

ENERAL

ESCRIPTION

The CH7010 is a display controller device which accepts a

digital graphics input signal, and encodes and transmits data

through a DVI (DFP can also be supported) or TV output

(analog composite, s-video or RGB). The device accepts data

over one 12-bit wide variable voltage data port which supports

five different data formats including RGB and YCrCb.

The DVI processor includes a low jitter PLL for generation of

the high frequency serialized clock, and all circuitry required

to encode, serialize and transmit data. The CH7010 comes in

versions able to drive a DVI display at a pixel rate of up to

165MHz, supporting UXGA resolution displays. No scaling

of input data is performed on the data output to the DVI

device.

The TV-Out processor performs non-interlace to interlace

conversion with scaling and flicker filters, and encode the data

into any of the NTSC or PAL video standards. The scaling and

flicker filter is adaptive and programmable to enable superior

text display. Eight graphics resolutions are supported up to

1024 by 768 with full vertical and horizontal underscan

capability in all modes. A high accuracy low jitter phase

locked loop is integrated to create outstanding video quality.

Support is provided for RGB bypass

mode which enables

driving a VGA CRT with the input data.

XCLK, XCLK*

Clock

Driver

DVI PLL

DVI

Encode

DVI

Serialize

DVI

Driver

TLC,TLC*

TDC0,TDC0*

TDC1,TDC1*

TDC2,TDC2*

VSWING

HPDET

GPIO[1:0]

SPC

SPD

RESET*

C/H SYNC

ISET

D[11:0]

Data

Latch,

Demux

H,V,DE

VREF

XI/FIN,XO

P-OUT/TLDET*

H, V, DE

Latch

PLL3

Serial

port

Control

BCO

Timing

Scaling

Scan

Conv

Flicker Filt

Four

10-bit

DAC’s

Encode

CVBS

(DAC3)

Y/G

(DAC1)

C/R

(DAC2)

CVBS/B

(DAC0)

Figure 1. Functional Block Diagram

201-0000-038

Rev 3.1, 11/4/2004

CHRONTEL

3. P

ESCRIPTIONS

3.1 Package Diagram

CH7010B

DGND

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

XCLK

XCLK*

D[6]

D[7]

D[8]

D[9]

D[10]

D[11]

DVDD

VREF

DGND

GPIO[1] / TLDET*

GPIO[0]

HPDET

DGND

DVDD

RESET*

SPD

SPC

AGND

C / H SYNC

BCO / V SYNC

P-OUT/TLDET*

DVDDV

AVDD

XI / FIN

AGND

GND

CVBS / B

C/R

Y/G

CVBS

ISET

GND

VDD

Chrontel

CH7010

AGND

AVDD

VSWING

TGND

TDC0*

TDC0

TVDD

TDC1*

TDC1

TGND

TDC2*

TDC2

Figure 2. 64-Pin LQFP

TVDD

TLC

TLC*

TGND

201-0000-038

Rev 3.1, 11/4/2004

CHRONTEL

3.2 Pin Description

Table 1. Pin Description

64-Pin # Pins Type

Symbol Description

LQFP

CH7010B

Data Enable

This pin accepts a data enable signal which is high when active video data

is input to the device, and low all other times. The levels are 0 to

DVDDV, and the VREF signal is used as the threshold level. This input is

used by the DVI. The TV-Out function uses H and V sync signals as

reference to active video.

VREF

Reference Voltage Input

The VREF pin inputs a reference voltage of DVDDV / 2. The signal is

derived externally through a resistor divider and decoupling capacitor,

and will be used as a reference level for data, sync, data enable and clock

inputs.

In/Out

Horizontal Sync Input / Output

When the SYO bit is low, this pin accepts a horizontal sync input for use

with the input data. The amplitude will be 0 to DVDDV, and the VREF

signal is used as the threshold level.

When the SYO bit is high, the device will output a horizontal sync pulse,

64 pixels wide. The output is driven from the DVDD. This output is only

for use with the TV-Out function.

In/Out

Vertical Sync Input / Output

When the SYO bit is low, this pin accepts a vertical sync input for use

with the input data. The amplitude will be 0 to DVDDV, and the VREF

signal is used as the threshold level.

When the SYO bit is high, the device will output a vertical sync pulse one

line wide. The output is driven from the DVDD supply. This output is

only for use with the TV-Out function.

In/Out

GPIO[1]

General Purpose Input - Output[1] /

TLDET*

DVI Detect Output

(Open drain or internal weak pull-up)

This pin provides a general purpose I/O controlled via the serial port.

When the GPIO[1] pin is configured as an output, this pin can be used to

output the DVI detect signal (pulls low when a termination change has

been detected on the

input). This is an open drain output. The output is released through

serial port control.

In/Out

GPIO[0]

General Purpose Input - Output[0]

(Open drain or internal weak pull-up)

This pin provides a general purpose I/O controlled via the serial port.

This allows an external switch to be used to select NTSC or PAL at

power-up.

HPDET

Hot Plug Detect

(internal pull-down)

This input pin determines whether the DVI is connected to a DVI

monitor. When terminated, the monitor is required to apply a voltage

greater than 2.4 volts. Changes on the status of this pin will be relayed to

the graphics controller via the P-OUT/TLDET* or GPIO[1]/TLDET* pin

pulling low.

When the HPDET is pulled low, the DVI output driver will be shut down.

Address Select

(Internal pull-up)

This pin determines

(1,1,1,0,1,AS*,AS).

the

serial

port

address

the

device

201-0000-038

Rev 3.1, 11/4/2004

CHRONTEL

Table 1. Pin Description

(continued)

64-Pin # Pins Type

Symbol Description

LQFP

RESET*

CH7010B

Reset * Input

(Internal pull-up)

When this pin is low, the device is held in the power-on reset condition.

When this pin is high, reset is controlled through the serial port register.

In/Out

SPD

Serial Port Data Input / Output

This pin functions as the serial port data pin of the serial port interface,

and uses the DVDD supply.

Serial Port Clock Input

This pin functions as the clock pin of the

serial port

interface, and uses

the DVDD supply.

VSWING

DVI Swing Control

This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor

should be connected between this pin and TGND using short and wide

traces.

SPC

22, 21

25, 24

Out

TDC0,

TDC0*

TDC1,

TDC1*

DVI Data Channel 0 Outputs

These pins provide the DVI differential outputs for data channel 0 (blue).

DVI Data Channel 1 Outputs

These pins provide the DVI differential outputs for data channel 1

(green).

28, 27

30, 31

Out

TDC2,

TDC2*

TLC,

TLC*

DVI Data Channel 2 Outputs

These pins provide the DVI differential outputs for data channel 2 (red).

DVI Clock Outputs

These pins provide the differential clock output for the DVI interface

corresponding to data on the TDC[0:2] outputs.

ISET

Current Set Resistor Input

This pin sets the DAC current. A 140 ohm resistor should be connected

between this pin and GND (DAC ground) using short and wide traces.

Out

CVBS

Composite Video

This pin outputs a composite video signal capable of driving a 75 ohm

doubly terminated load.

Out

Y/G

Luma / Green Output

This pin outputs a selectable video signal. The output is designed to drive

a 75 ohm doubly terminated load. The output can be selected to be s-

video luminance or green.

Out

C/R

Chroma / Red Output

This pin outputs a selectable video signal. The output is designed to drive

a 75 ohm doubly terminated load. The output can be selected to be s-

video chrominance or red.

Out

CVBS/B

Composite Video / Blue Output

This pin outputs a selectable video signal. The output is designed to drive

a 75 ohm doubly terminated load. The output can be selected to be

composite video or blue.

XI / FIN

Crystal Input / External Reference Input

A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached

between this pin and XO. However, an external clock can drive the

XI/FIN input.

64-Pin # Pins Type

LQFP

Symbol Description

201-0000-038

Rev 3.1, 11/4/2004

CHRONTEL

Table 1. Pin Description

(continued)

CH7010B

Crystal Output

A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached

between this pin and XI / FIN. However, if an external CMOS clock is

attached to XI/FIN, XO should be left open.

Out

P-OUT /

TLDET*

Pixel Clock Output / DVI Detect Output

When the CH7010 is operating as a VGA to TV encoder in master clock

mode, this pin provides a pixel clock signal to the VGA controller which

is used as a reference frequency. The output is selectable between 1X or

2X of the pixel clock frequency. The output driver is driven from the

DVDDV supply. This output has a programmable tri-state. The

capacitive loading on this pin should be kept to a minimum.

When the CH7010 is operating as a DVI transmitter, this pin provides an

open drain output which pulls low when a termination change has been

detected on the HPDET input. The output is released through serial port

control.

Out

BCO/

V SYNC

Buffered Clock Output / Vertical Sync Output

This output pin provides a buffered clock output, driven by the DVDD

supply. The output clock can be selected using the BCO register.

This pin can also be used as VSYNC output.

Out

C/H

SYNC

Composite / Horizontal Sync Output

This pin can be selected to output a TV composite sync, TV horizontal

sync, or a buffered version of the VGA horizontal sync. The output is

driven from the DVDD supply.

50 – 55,

58 – 63

57, 56

In / Out

D[11] -

D[0]

XCLK,

XCLK*

Data[11] through Data[0] Inputs

These pins accept the 12 data inputs from a digital video port of a

graphics controller. The levels are 0 to DVDDV, and the VREF signal

is used as the threshold level.

External Clock Inputs

These inputs form a differential clock signal input to the CH7010 for

use with the H, V, DE and D[11:0] data. If differential clocks are not

available, the XCLK* input should be connected to VREF.

The output clocks from this pad cell are able to have their polarities

reversed under the control of the MCP bit (in register 1Ch).

Digital Supply Voltage (3.3V-3.6V)

Digital Ground

I/O Supply Voltage (3.3V to 1.1V)

DVI Transmitter Supply Voltage (3.3V-3.6V)

DVI Transmitter Ground

1, 12, 49

6, 11, 64

23, 29

20, 26,

18, 44

16, 17,

34, 40

Power

DVDD

DGND

DVDDV

TVDD

TGND

AVDD

AGND

VDD

GND

PLL Supply Voltage

PLL Ground

DAC Supply Voltage

DAC Ground

(3.3V-3.6V)

201-0000-038

Rev 3.1, 11/4/2004

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