CY7C386P-XGMB datasheet, PDF - EEWORLD Datasheet

CY7C386P-XGMB: DescriptionField Programmable Gate Array, 384 CLBs, 4000 Gates, 107.5MHz, 384-Cell, CMOS, CPGA145, CAVITY UP, CERAMIC, PGA-145; CategoryProgrammable logic devices Programmable logic; File Size318KB，12 Pages; ManufacturerCypress Semiconductor

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CY7C386P-XGMB Overview

Field Programmable Gate Array, 384 CLBs, 4000 Gates, 107.5MHz, 384-Cell, CMOS, CPGA145, CAVITY UP, CERAMIC, PGA-145

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	PGA
package instruction	CAVITY UP, CERAMIC, PGA-145
Contacts	145
Reach Compliance Code	not_compliant
ECCN code	3A001.A.2.C
Other features	MAX 114 I/OS; OTP BASED
maximum clock frequency	107.5 MHz
Combined latency of CLB-Max	15.9 ns
JESD-30 code	S-CPGA-P145
JESD-609 code	e0
length	40.0685 mm
Configurable number of logic blocks	384
Equivalent number of gates	4000
Number of entries	122
Number of logical units	384
Output times	114
Number of terminals	145
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	384 CLBS, 4000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA144,15X15
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.207 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	40.0685 mm

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