M53D128168A-10BG datasheet, PDF

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M53D128168A-10BG: DescriptionDDR DRAM, 8MX16, 9ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, BGA-60; Categorystorage storage; File Size1MB，47 Pages; ManufacturerESMT; Websitehttp://www.esmt.com.tw/; Elite Semiconductor Memory Technology Inc. (ESMT) is a professional IC design company founded by Dr. Hu Zhao in June 1998. Its headquarters is located in Hsinchu Science Park, Taiwan. The company's main business includes research, development, manufacturing, sales and related technical services of IC products. It was listed on the Taiwan Stock Exchange in March 2002.

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M53D128168A-10BG Overview

DDR DRAM, 8MX16, 9ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, BGA-60

M53D128168A-10BG Parametric

Parameter Name	Attribute value
Parts packaging code	BGA
package instruction	VFBGA,
Contacts	60
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	9 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
length	10 mm
memory density	134217728 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm
Base Number Matches	1

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ESMT

Mobile DDR SDRAM

Preliminary

M53D128168A

2M x 16 Bit x 4 Banks

Mobile

DDR SDRAM

Features

JEDEC Standard

Internal pipelined double-data-rate architecture, two data

access per clock cycle

Bi-directional data strobe (DQS)

No DLL; CLK to DQS is not synchronized.

Differential clock inputs (CLK and CLK )

Quad bank operation

CAS Latency : 2, 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

Special function support

PASR (Partial Array Self Refresh)

Internal TCSR (Temperature Compensated Self

Refresh)

DS (Driver Strength)

All inputs except data & DM are sampled at the rising

edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for READ; center-aligned

with data for WRITE

Data mask (DM) for write masking only

DDQ

= 1.7V ~ 1.9V

Auto & Self refresh

15.6us refresh interval (64ms refresh period, 4K cycle)

1.8V LVCMOS-compatible inputs

60 ball BGA package

Ordering information :

Part NO.

M53D128168A -7.5BG

M53D128168A -10BG

M53D128168A -7.5BAG

M53D128168A -10BAG

MAX FREQ

133MHz

100MHz

133MHz

100MHz

1.8V

VDD

PACKAGE

8x10 mm

BGA

8x13 mm

BGA

COMMENTS

Pb-free

Functional Block Diagram

CLK

CKE

Address

Mode Register &

Extended Mode

Clock

Generator

Bank D

Bank C

Bank B

Row Decoder

Row

Address

Buffer

Refresh

Counter

Bank A

DQS

Sense Amplifier

CAS

Data Control Circuit

Input & Output

Buffer

Latch Circuit

RAS

Control Logic

Command Decoder

Column

Address

Buffer

Refresh

Counter

Column Decoder

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2008

Revision : 1.4

1/47

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