UTRON
Rev. 1.3
UT62L25716(I)
256K X 16 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
DESCRIPTION
Preliminary Rev. 0.5
Original.
Rev.1.0
1.Separate Industrial and Commercial SPEC.
2.New waveforms.
3.Add access time 55ns range.
4.The symbols CE1# and OE# and WE# are revised as. CE1 and
OE and
WE
.
Rev.1.1
1.Revised access time 55/70/100ns
-Rev 1.0: 55ns(max) for Vcc=3.0V~3.6V
70/100 ns(max) for Vcc=2.7V~3.6V
2.Revised “SYMBOL” : CE1 CE
3.Revised ABSOLUTE MAXIMUM RATINGS
- V
TERM
: -0.3 to 4.6
-0.5 to 4.6V
- P
D :
1.0~1.5
1W
- I
OUT
: 50 20mA
4.Revised DC CHARACTERISTICS
- V
IH
: 2.0 2.2V
5.Revised AC CHARACTERISTICS
- t
OH
& t
BLZ
: 5 10ns
6.Revised 48-pin TFBGA package outline dimension：
-ball diameter : 0.3mm
0.35mm
Rev.1.2
1. Revised Standby current (LL-Version) : 3uA(typ) 2uA(typ)
2. Revised operating current (Iccmax) : 45/35/25mA 40/30/25mA
3. Revised DC CHARACTERISTICS :
a. Operating Power Supply Current (Icc)
55ns (max) : 45 40mA
70ns (typ) : 25 20mA, 70ns (max) : 35 30mA
100ns (Typ) : 20 16mA
b. Standby current(CMOS) :
LL-version (typ) : 3 2uA, 25 20uA
Rev.1.3
1. Revised V
OH
(Typ) : NA 2.7V
2. Add V
IH
(max)=V
CC
+2.0V for pulse width less than 10ns.
V
IL
(min)=V
SS
-2.0V for pulse width less than 10ns.
3. Add order information for lead free product
Draft Date
Mar, 2001
Aug 7,2001
Nov 8 ,2002
Dec 3,2002
May 6,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
1
UTRON
Rev. 1.3
UT62L25716(I)
256K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L25716(I) is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
The UT62L25716(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT62L25716(I) is designed for low power
system applications. It is particularly well suited for
use in high-density low power system applications.
FEATURES
Fast access time : 55/70/100ns
CMOS low power operating
Operating current : 40/30/25 (Icc,max.)
Standby current : 20uA (TYP.) L-version
2uA (TYP.) LL-version
Single 2.7V~3.6V power supply
Operation temperature:
Industrial : -40
℃
~85
℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage:1.5V (min.)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 48-pin 6mm × 8mm TFBGA
FUNCTIONAL BLOCK DIAGRAM
256K X 16
MEMORY
ARRAY
A0-A17
DECODER
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O9-I/O16
Upper Byte
I/O DATA
CIRCUIT
COLUMN I/O
CE2
CE
OE
WE
LB
UB
CONTROL
CIRCUIT
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
2
UTRON
Rev. 1.3
UT62L25716(I)
256K X 16 BIT LOW POWER CMOS
PIN DESCRIPTION
SYMBOL
A0 - A17
I/O1 - I/O16
CE , CE2
WE
OE
LB
UB
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-byte Control
Upper-byte Control
Power Supply
Ground
No Connection
SRAM
PIN CONFIGURATION
A
LB
OE
A0
A1
A2
CE2
B
I/O9
UB
A3
A4
CE
I/O1
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
Vss
I/O12
A17
A7
I/O4
Vcc
E
Vcc
I/O13
NC
A16
I/O5
Vss
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
NC
A12
A13
WE
I/O8
H
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
TFBGA
TRUTH TABLE
MODE
CE
CE2
OE
WE
LB
UB
X
X
H
X
L
H
L
L
H
L
L
H
X
X
Standby
X
L
X
X
X
X
L
H
H
Output Disable
L
H
H
L
H
L
Read
L
H
L
L
H
L
L
H
X
Write
L
H
X
L
H
X
Note: H = V
IH
, L=V
IL
, X = Don't care.
X
X
X
H
H
H
H
H
L
L
L
X
X
H
L
X
L
H
L
L
H
L
I/O OPERATION
I/O1-I/O8
I/O9-I/O16
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
High – Z
D
OUT
D
OUT
High – Z
D
OUT
D
OUT
D
IN
High – Z
D
IN
High – Z
D
IN
D
IN
SUPPLY
CURRENT
I
SB
, I
SB1
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
I
CC
,I
CC1
,I
CC2
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
3
UTRON
Rev. 1.3
UT62L25716(I)
256K X 16 BIT LOW POWER CMOS SRAM
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 4.6
-40 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
W
mA
℃
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vcc = 2.7V~3.6V, T
A
= -40
℃
to 85
℃
(I))
PARAMETER
SYMBOL
TEST CONDITION
Power Voltage
V
CC
＊
1
Input High Voltage
V
IH
＊
2
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
SS
≦
V
IN
≦
V
CC
Output Leakage Current
I
LO
V
SS
≦
V
I/O
≦
V
CC;
Output Disable
Output High Voltage
V
OH
I
OH
= -1mA
Output Low Voltage
V
OL
I
OL
= 2.1mA
Cycle time=min, 100%duty
Operating Power
I
CC
I/O=0mA, CE =V
IL
Supply Current
Average Operation
Current
Standby Current (TTL)
Standby Current (CMOS)
I
CC1
I
CC2
I
SB
I
SB1
CE =V
IH,
other pins =V
IL
or V
IH
CE =V
CC
-0.2V
other pins at 0.2V or Vcc-0.2V
100%duty,I
I/O
=0mA, CE
≦
0.2V,
other pins at 0.2V or Vcc-0.2V
MIN. TYP. MAX. UNIT
2.7 3.0
3.6
V
V
2.2
-
V
CC
+0.3
-0.2
-
0.6
V
-1
-
1
µA
-1
-
1
µA
2.2 2.7
-
V
-
-
0.4
V
-
30
40
mA
-
20
30
mA
-
16
25
mA
-
-
-
-
-
4
8
0.3
20
2
5
10
0.5
80
20
mA
mA
mA
µA
µA
55
70
100
Tcycle=
1µs
Tcycle=
500ns
-L
-LL
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
4
UTRON
Rev. 1.3
UT62L25716(I)
256K X 16 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 30pF, I
OH
/I
OL
= -1mA/2.1mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V~3.6V , T
A
= -40
℃
to 85
℃
(I))
(1) READ CYCLE
SYMBOL
UT62L25716(I)-55
MIN.
MAX.
Read Cycle Time
t
RC
55
-
Address Access Time
t
AA
-
55
Chip Enable Access Time
t
ACE
-
55
Output Enable Access Time
t
OE
-
30
Chip Enable to Output in Low Z
t
CLZ*
10
-
Output Enable to Output in Low Z
t
OLZ*
5
-
Chip Disable to Output in High Z
t
CHZ*
-
20
Output Disable to Output in High Z
t
OHZ*
-
20
Output Hold from Address Change
t
OH
10
-
t
BA
-
55
LB
,
UB
Access Time
t
BHZ
-
25
LB
,
UB
to High-Z Output
t
BLZ
10
-
LB
,
UB
to Low-Z Output
(2) WRITE CYCLE
SYMBOL
UT62L25716(I)-55
MIN.
MAX.
Write Cycle Time
t
WC
55
-
Address Valid to End of Write
t
AW
50
-
Chip Enable to End of Write
t
CW
50
-
Address Set-up Time
t
AS
0
-
Write Pulse Width
t
WP
45
-
Write Recovery Time
t
WR
0
-
Data to Write Time Overlap
t
DW
25
-
Data Hold from End of Write Time
t
DH
0
-
Output Active from End of Write
t
OW*
5
-
Write to Output in High Z
t
WHZ*
-
30
t
BW
45
-
LB
,
UB
Valid to End of Write
PARAMETER
UT62L25716(I)-70
UT62L25716(I)-100
UNIT
PARAMETER
UT62L25716(I)-70
UT62L25716(I)-100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
70
-
-
-
10
5
-
-
10
-
-
10
MAX.
-
70
70
35
-
-
25
25
-
70
30
-
MIN.
100
-
-
-
10
5
-
-
10
-
-
10
MAX.
-
100
100
50
-
-
30
30
-
100
40
-
MIN.
70
60
60
0
55
0
30
0
5
-
60
MAX.
-
-
-
-
-
-
-
-
-
30
-
MIN.
100
80
80
0
70
0
40
0
5
-
80
MAX.
-
-
-
-
-
-
-
-
-
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80046
5
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