EL2006CG is an OPERATIONAL AMPLIFIER. Commonly used packaging methods are QIP, QUAD12,.4SQ
EL2006CG amplifier core information:
The minimum operating temperature of EL2006CG is -25 °C and the maximum operating temperature is 85 °C. Maximum bias current at 25°C: 0.0005 µA
The maximum slew rate of the EL2006CG given by the manufacturer is 23 mA, while the minimum slew rate is 350 V/us. Its minimum voltage gain is 5000. When the op amp is used in closed loop, at a certain closed-loop gain (usually 1 or 2, 10, etc.), the frequency when the EL2006CG gain becomes 0.707 times the low-frequency gain is 500000 kHz.
The nominal supply voltage of EL2006CG is 15 V, and its corresponding nominal negative supply voltage is -15 V. The power supply range is: +-15 V. The input offset voltage of EL2006CG is 10000 µV (input offset voltage: the compensation voltage added between the two input terminals to make the output terminal of the operational amplifier 0V (or close to 0V).)
Related dimensions of EL2006CG:
EL2006CG has 12 terminals. Its terminal position type is: QUAD. Terminal pitch is 2.54 mm. Total pins: 12
EL2006CG amplifier additional information:
EL2006CG adopts the VOLTAGE-FEEDBACK architecture. It belongs to the low-bias class of amplifiers. It does not belong to the low offset class of amplifiers. The frequency compensation status of EL2006CG is: NO. Its temperature grade is: OTHER.
The corresponding JESD-30 code is: S-MQIP-T12. The packaging code of EL2006CG is: QIP. The materials used in EL2006CG packaging are mostly METAL. The package shape is SQUARE. The EL2006CG package pin format is: IN-LINE.
EL2006CG is an OPERATIONAL AMPLIFIER. Commonly used packaging methods are QIP, QUAD12,.4SQ
EL2006CG amplifier core information:
The minimum operating temperature of EL2006CG is -25 °C and the maximum operating temperature is 85 °C. Maximum bias current at 25°C: 0.0005 µA
The maximum slew rate of the EL2006CG given by the manufacturer is 23 mA, while the minimum slew rate is 350 V/us. Its minimum voltage gain is 5000. When the op amp is used in closed loop, at a certain closed-loop gain (usually 1 or 2, 10, etc.), the frequency when the EL2006CG gain becomes 0.707 times the low-frequency gain is 500000 kHz.
The nominal supply voltage of EL2006CG is 15 V, and its corresponding nominal negative supply voltage is -15 V. The power supply range is: +-15 V. The input offset voltage of EL2006CG is 10000 µV (input offset voltage: the compensation voltage added between the two input terminals to make the output terminal of the operational amplifier 0V (or close to 0V).)
Related dimensions of EL2006CG:
EL2006CG has 12 terminals. Its terminal position type is: QUAD. Terminal pitch is 2.54 mm. Total pins: 12
EL2006CG amplifier additional information:
EL2006CG adopts the VOLTAGE-FEEDBACK architecture. It belongs to the low-bias class of amplifiers. It does not belong to the low offset class of amplifiers. The frequency compensation status of EL2006CG is: NO. Its temperature grade is: OTHER.
The corresponding JESD-30 code is: S-MQIP-T12. The packaging code of EL2006CG is: QIP. The materials used in EL2006CG packaging are mostly METAL. The package shape is SQUARE. The EL2006CG package pin format is: IN-LINE.
The EL2006 EL2006A are high slew rate wide bandwidth high
input impedance high gain and fully differential input opera-
tional amplifiers They exhibit excellent open loop gain charac-
teristics making them suitable for a broad range of high speed
signal processing applications These patented devices have
open loop gains in excess of 86 dB making the EL2006
EL2006A ideal choices for current mode video bandwidth digi-
tal to analog converters of 10 bits or higher resolution The
EL2006’s FET input structure high slew rate and high output
drive capability allow use in applications such as buffers for
flash converter inputs In general the EL2006 EL2006A allow
the user to take relatively high closed loop gains without com-
promising gain accuracy or bandwidth
The EL2006 EL2006A are pin compatible with the popular in-
dustry standard ELH0032 ELH0032A offering comparable
bandwidth and slew rate while offering significant improve-
ments in open loop gain common mode rejection and power
supply rejection
Elantec facilities comply with MIL-I-45208A and are
MIL-STD-1772 certified Elantec’s Military devices comply
with MIL-STD-883 Class B Revision C and are manufactured
in our rigidly controlled ultra-clean facilities in Milpitas Cali-
fornia For additional information on Elantec’s Quality and Re-
liability Assurance Policy and procedures request brochure
QRA-1
Ordering Information
Part No
EL2006CG
EL2006G
EL2006G 883B
EL2006ACG
EL2006AG
EL2006AG 883G
Temp Range
b
25 C to
a
85 C
b
55 C to
a
125 C
b
55 C to
a
125 C
b
25 C to
a
85 C
b
55 C to
a
125 C
b
55 C to
a
125 C
Pkg
TO-8
TO-8
TO-8
TO-8
TO-8
TO-8
Outline
MDP0002
MDP0002
MDP0002
MDP0002
MDP0002
MDP0002
Connection Diagrams
Simplified Schematic
2006 – 1
Top View
November 1993 Rev F
2006 – 3
Manufactured under U S Patent No 4 746 877
Note
All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
1989 Elantec Inc
EL2006 EL2006A
High Gain Fast FET Input Op Amp
Absolute Maximum Ratings
(T
A
e
25 C)
V
S
V
IN
I
OUT
P
D
g
18V
Supply Voltage
g
15V
Input Voltage
Differential Input Voltage
30V
g
200 mA
Peak Output Current (Note 1)
Power Dissipation
T
A
e
25 C 1 5W derate 100 C W to
a
125 C
T
C
e
25 C 2 2W derate 70 C W to
a
125 C
T
A
b
65 C to
a
150 C
300 C
Important Note
All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually
performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test
equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore T
J
e
T
C
e
T
A
Test Level
I
II
III
IV
V
Test Procedure
100% production tested and QA sample tested per QA test plan QCX0002
100% production tested at T
A
e
25 C and QA sample tested at T
A
e
25 C
T
MAX
and T
MIN
per QA test plan QCX0002
QA sample tested per QA test plan QCX0002
Parameter is guaranteed (but not tested) by Design and Characterization Data
Parameter is typical value at T
A
e
25 C for information purposes only
DC Electrical Characteristics
V
S
e
g
15V
Parameter
V
OS
Description
Offset Voltage
Test Conditions
T
J
e
25 C
T
MIN
k
T
A
k
T
MAX
EL2006
Min
Typ Max
5
10
Test
Level
I
I
V
100
1
10
25
02
25
I
I
I
I
I
80
88
90
I
I
I
I
I
I
20
23
I
g
10
EL2006C
Min
Typ Max
5
10
15
500
1
10
50
02
25
Test Units
Level
I
III
V
I
III
I
III
II
80
88
90
II
II
I
III
II
I
20
23
II
mV
mV
mV
C
pA
nA
pA
nA
V
dB
dB
dB
dB
V
mA
mA
TD is 3 9in
DV
OS
DT
I
B
Offset Voltage Drift
Bias Current
T
J
e
25 C
15
I
OS
Offset Current
T
J
e
25 C
V
CM
CMRR
PSRR
A
VOL
Common Mode Range
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large Signal
Voltage Gain
DV
IN
e
g
10V
g
5V
s
V
S
s g
15V
g
10
70
70
74
80
g
12
g
100
70
70
74
74
g
12
g
100
R
L
e
1 kX V
OUT
e
g
10V
T
J
e
25 C
R
L
e
1 kX V
OUT
e
g
10V
V
O
I
OUT
I
CC
Output Voltage Swing R
L
e
1 kX
Output Current
Supply Current
V
OUT
e
g
10V
T
J
e
25 C (Note 1)
2
TD is 0 9in
T
J
T
ST
Operating Temperature Range
EL2006 EL2006A
EL2006C EL2006AC
Operating Junction Temperature
Storage Temperature
Lead Temperature
(Soldering 10 seconds)
b
55 C to
a
125 C
b
25 C to
a
85 C
175 C
EL2006 EL2006A
High Gain Fast FET Input Op Amp
DC Electrical Characteristics
Contd
EL2006A
Parameter
V
OS
DV
OS
DT
A
VOL
Description
Offset Voltage
Offset Voltage Drift
Large Signal
Voltage Gain
T
J
e
25 C R
L
e
1 kX
V
OUT
e
g
10V
R
L
e
1 kX V
OUT
e
g
10V
74
74
Test Conditions
T
J
e
25 C
15
90
Min Typ Max
3
25
EL2006AC
Test
Test
Min Typ Max
Level
Level
I
I
I
I
74
74
15
90
3
25
I
I
II
III
Units
mV
mV
C
dB
dB
TD is 1 4in
TD is 2 9in
V
S
e
g
15V T
MIN
k
T
A
k
T
MAX
(Note These tests are in addition to those listed above )
AC Electrical Characteristics
V
S
e
g
15V
Parameter
t
r
Description
Rise Time
Test Conditions
R
L
e
1 kX T
J
e
25 C (See AC Test Circuits)
EL2006 EL2006A
Min Typ Max
18
12
350
450
90
160
250
500
55
7
40
20
13
2
15
15
EL2006C EL2006AC
Units
ns
ns
V
ms
ns
ns
ns
MHz
MHz
MHz
nV
0
Hz
ns
pF
Test
Test
Min Typ Max
Level
Level
V
I
I
V
V
V
V
I
V
V
I
V
55
350
18
12
450
90
160
250
500
7
40
20
13
2
15
15
V
I
I
V
V
V
V
I
V
V
I
V
A
V
e
10V V
OUT
e
1 V
P-P
A
V
e
1V V
OUT
e
1 V
P-P
SR
t
s
t
s
t
s
GBW
Slew Rate (Note 2)
Settling Time to 1 0%
Settling Time to 0 1%
Settling Time to 0 01%
A
V
e
1V V
OUT
e
20 V
P-P
A
V
e b
1V V
OUT
e
10 V
P-P
A
V
e b
1V V
OUT
e
10 V
P-P
A
V
e b
1V V
OUT
e
10 V
P-P
Gain Bandwidth Product A
V
t
20V
Pull Power
Bandwidth (Note 3)
Unity Gain Bandwidth
V
OUT
e
g
10V
C
A
e
8 pF C
B
e
100 pF
1 kHz to 1 MHz
A
V
e
1V
e
N
t
D
C
IN
Noise Voltage
Small Signal Delay
Input Capacitance
Note 1 T
J
e
25 C duty cycle
k
1% pulse width
k
10
ms
Note 2 Slew rate is measured at the 25% and 75% points
Note 3 The Full Power bandwidth is guaranteed by testing slew rate
EL2006 Recommended Compensation
(See Figure 1)
A
VOL
a
1
b
1 to
a
5
g
10
l g
20
C
A
5–8 pF
5 pF
5 pF
3 pF
C
B
100 pF
68 pF
10 pF
10 pF
R
S
a
2k
0
k
1k
k
1k
R
S
b
Open Circuit
k
1k
R
F
100
1k
l
10k
l
20k
1k
1k
Note Use a small capacitor of about 1 pF in parallel with R
F
to compensate for stray
input capacitance
2006 – 4
Figure 1
3
EL2006 EL2006A
High Gain Fast FET Input Op Amp
Typical Performance Curves
Bode Plot Unity Gain
Compensation
Supply Current vs
Temperature
Inverting Gain of
b
1
Settling Time
Input Bias Currents as a
Function of Input
Voltage
TO-8
Maximum Power
Dissipation
Normalized Input Bias
and Offset Current vs
Junction Temperature
2006 – 5
Applications Information
General
The EL2006 was designed to overcome the gain
and stability limitations of prior high speed FET
input operational amplifiers like the LH0032
Open loop gain is typically 90 dB allowing gain
setting to 12-bit accuracy This new design also
eliminates ‘‘thermal tail’’ which is the tendency
for the gain to diminish at very low frequencies
to DC due to thermal feedback The EL2006 is
also easier to stabilize than earlier designs
thanks to an Elantec proprietary internal com-
pensation technique which eliminates the ‘‘sec-
ond stage bump ’’ The EL2006 open loop gain
4
EL2006 EL2006A
High Gain Fast FET Input Op Amp
Applications Information
Contd
characteristic is well behaved well beyond the
unity gain frequency so that spurious ringing or
oscillation in the 100 MHZ – 200 MHz region is
avoided Finally we have provided temperature
compensation so that gain and stability are rela-
tively constant over temperature
These improvements are provided in a configura-
tion which is plug compatible with LH0032 and
similar products so that designers can easily up-
grade their system performance without exten-
sive re-design In most cases the EL2006 can be
used to replace LH0032 with no change in exter-
nal compensation
Power Dissipation
There is an additional effect on input bias current
as the input voltage is changed The effect com-
mon to all FETs is an avalanche-like increase in
gate current as the FET gate-to-drain voltage is
increased above a critical value depending on
FET geometry and doping levels This effect will
be noted as the input voltage of the EL2006 is
taken below ground potential when the supplies
are
g
15V All of the effects described here may
be minimized by operating the device with
V
S
s g
15V
These effects are indicated in the typical per-
formance curves
Video DAC Amplifiers
A typical application for the EL2006 is to pro-
vide gain for video signals In the example
shown the EL2006 provides a gain of 2 with set-
tling time around 35 ns to 10 mV
Input Capacitance
The input capacitance to the EL2006 EL2006A
is typically 2 pF and thus may form a significant
time constant with high value resistors For opti-
mum performance the input capacitance to the
inverting input should be compensated by a
small capacitor across the feedback resistor The
value is strongly dependent on layout and closed
loop gain but will typically be in the neighbor-
hood of several picofarads
In the non-inverting configuration it may be ad-
vantageous to bootstrap the case and or a guard
conductor to the inverting input This serves
both to divert leakage currents away from the
non-inverting input and to reduce the effective
input capacitance A unity gain follower so treat-
ed will have an input capacitance under a 1 pF
Power Supply Decoupling
The EL2006 EL2006A like most high-speed cir-
cuits is sensitive to layout and stray capacitance
Power supplies should be bypassed as near to
pins 10 and 12 as possible with low inductance
capacitors such as 0 01
mF
disc ceramics Com-
pensation components should also be located
close to the appropriate pins to minimize stray
reactances
Input Current
Because the input devices are FETs the input
bias current may be expected to double for each
11 C junction temperature rise This characteris-
tic is plotted in the typical performance charac-
teristics graphs The device will self-heat due to
internal power dissipation after application of
power thus raising the FET junction tempera-
ture 40 C– 60 C above the free-air ambient tem-
perature when supplies are
g
15V The device
temperature will stabilize within 5 –10 minutes
after application of power and the input bias cur-
rents measured at the time will be indicative of
normal operating currents An additional rise will
occur as power is delivered to a load due to addi-
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