Implementing SPWM using TMS320LF2407

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Implementing SPWM using TMS320LF2407 [Copy link]

The so-called SPWM is PWM in which the pulse width changes according to the sine law. According to the sampling theory: the effect of narrow pulses with equal impulses but different shapes added to the inertial link is basically the same. It can be seen that in order to obtain a sine wave at the output end, it is necessary to output a series of rectangular waves with equal amplitudes but different widths. By adopting the regular sampling method of the triangular carrier, a rectangular wave with a width that changes according to the sine law can be obtained. As shown in Figure 3, the midpoint of each pulse is symmetrical with the midpoint of the corresponding triangular wave. At the negative peak time TD of the triangular carrier, the sine wave is sampled to obtain point D. A horizontal straight line is drawn through point D and the triangular wave intersects at points A and B respectively. At point A time tA and point B time tB, the power device is controlled to be on and off. It can be seen that the length AB is the pulse width. From the figure, the following relationship can be obtained: AB=Tc(1+sinωctD)/2 (2) According to this relationship, if there are N rectangular waves in one cycle, the duty cycle of the Ith rectangular wave is: 355813 4.2 Using TMS320LF2407 to implement SPWM control Here, the general timer 3 in EVB and its related comparison unit are used as an example to illustrate the process of implementing SPWM control. The three timers of EVB in TMS320LF2407 have three associated comparison units: comparison units 4, 5, and 6. Each comparison unit has a corresponding comparison register: CMPR4, CMPR5, and CMPR6. Each comparison unit can be set to comparison mode and PWM mode individually. When set to PWM mode, each comparison unit has two PWM outputs with opposite polarities. Therefore, TMS320LF2407 can be used to realize SPWM control of three-phase bridge inverter circuit. When the value of period register T3PR is constant, the width of the output rectangular pulse can be changed by changing the value of the comparison register [3]. According to the duty cycle expression obtained by formula (3), and then using the PWM characteristics of the general timer comparison unit, SPWM can be easily realized. First, the register setting for generating PWM is introduced. The steps are as follows: (1) Load the comparison mode control register ACTRB. (2) If the dead zone is enabled, set and load the dead zone time control register DBTCONB (if enabled, it can avoid the upper and lower bridge arms from outputting trigger pulses at the same time.) (3) Set and load the timer 3 period register, that is, specify the PWM waveform period. (4) Initialize the EVB comparison registers CMPR4, CMPR5, and CMPR6. (5) Set and load the timer 3 control register T3CON. (6) Update the value of the comparison register to change the duty cycle of the output PWM waveform. The specific program design method is as follows: (1) After the system is initialized, the number of rectangular waves that need to be output in each cycle is calculated based on the carrier frequency and the signal frequency, thereby determining the cycle of the timer to set the frequency parameters and the number of pulses. (2) According to formula (3), the duty cycle of each rectangular pulse is calculated, and the duty cycle is multiplied by the value of the period register to calculate the value of the comparison register. This process is used as a calculation subroutine, and the number of pulse pointers I is increased by 1. (3) In the periodic interrupt subroutine, the calculated value of the comparison register is sent to the comparison register, and the corresponding flag is set when a carrier cycle is reached. Design and working principle analysis and simulation verification of PWM switching power supply based on DSP (4) The main program determines whether a cycle of operation has been completed based on the flag bit. If the flag bit TC is set to 1, the flag bit is cleared, the duty cycle calculation subroutine is called, and then the waiting state is entered; if the flag bit is not set to 1, the waiting state is entered directly.