Detailed introduction of vivado calling IP core

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Detailed introduction of vivado calling IP core [Copy link]

Everyone, it's time for daily learning again. Today, let's talk about vivado calling IP cores. First, let's take a look at vivado's IP cores. IP cores (IP Core): There are many IP cores in Vivado that can be used directly, such as mathematical operations (multipliers, dividers, floating-point operators, etc.) and signal processing (FFT, DFT, DDS, etc.). IP cores are similar to function libraries in programming (such as printf() functions in C language). They can be called directly, which is very convenient and greatly speeds up the development speed. Using Verilog to call IP cores Here is a simple example of using the IP core of a multiplier, using Verilog to call. First, create a new project and create a demo.v top-level module. 1. Add IP cores 1. Click IP Catalog in Flow Navigator. 2. Select Multiplier under Math Functions, that is, multiplier, and double-click. 3. The parameter setting dialog box for the IP core will pop up. Click Documentation in the upper left corner to open the user manual of this IP core for reference. Here, directly set the input signals A and B to 4-bit unsigned data, and the others to default values, and click OK. 4. Click Generate in the window that pops up later. 2. Call IP core 1. Select IP Sources, expand and select mult_gen_0 - Instantiation Template - mult_gen_0.veo to open the instantiation template file. As shown in the figure, this code is the sample code for calling this IP core using Verilog. 2. Copy the sample code to the demo.v file and modify it. The final result is as follows. The code declares unsigned 4-bit variables a and b, assigning initial values of 7 and 8 respectively, which are used as multipliers; the unsigned 8-bit variable p is used to save the calculation result. clk is a clock signal with a period of 20ns written by Testbench; the mult_gen_0 mul(...) statement instantiates the module object mul of type mult_gen_0, and passes clk, a, b, and p as parameters. 3. Behavioral simulation verification Take demo as the top-level module, start behavioral simulation, and the waveform can be output. Set a, b, and p to display as unsigned decimal (right-click and select Radix - Unsigned Decimal). As shown in the figure, we can see that a=7, b=8, and p = a * b = 56 after the first clock rising edge. Calling IP core in block diagram (Block Design) Here is a simple example. By calling the multiplier IP core, a new module that can calculate square is generated. 1. Create a block diagram design file 1. Select Create Block Design in Flow Navigator to create a block diagram design file. 2. Enter the file name and click OK. 2. Add IP core 1. Right-click in the blank area of the block diagram and select Add IP. 2. You can directly search for the required IP core and double-click to confirm. 3. The IP core can be added and can be connected to other devices with wires. 4. Double-click the IP core symbol to open the parameter setting dialog box. Click Documentation in the upper left corner to view the manual of the IP core. Here, set the input A and B to 4 for unsigned type, and the others to the default value, and click OK to confirm. 3. Draw the circuit 1. Right-click in the blank area of the Diagram window and select Create Port. 2. In the pop-up window, set port a to a 4-bit input signal and click OK. 3. Connect a to both A and B. 4. In the same way, add an 8-bit output port p and connect it to P. 5. Add a clk clock input port and connect it to CLK. 6. The final result is shown in the figure. IV. Simulation Test 1. Right-click the block diagram design file design_1 and select Create HDL Wrapper. 2. Select the second option and click OK. 3. Open the generated design_1_wrapper.v file as shown in the figure. The code in the red box is used to call the Block Design module drawn earlier. 4. In the design_1_wrapper.v file, add the Testbench code to perform behavioral simulation. Modify the code as follows, assign the initial value of 8 to the input signal a, and connect clk to the clock signal c generated by the Testbench. 5. In the Simulation Sources folder, set design_1_wrapper.v as the top-level file of the behavioral simulation (right-click and select Set as Top). Start the behavioral simulation, and the final output waveform is as follows. It can be seen that after the first rising edge of clk, p = a*a = 64, which means that the square operation is implemented.

大辉哥0614

Everyone, it's time for daily learning again. Today, let's talk about vivado calling IP cores. First, let's take a look at vivado's IP cores. IP cores (IP Core): There are many IP cores in Vivado that can be used directly, such as mathematical operations (multipliers, dividers, floating-point operators, etc.) and signal processing (FFT, DFT, DDS, etc.). IP cores are similar to function libraries in programming (such as printf() functions in C language). They can be called directly, which is very convenient and greatly speeds up the development speed. Using Verilog to call IP cores Here is a simple example of using the IP core of a multiplier, using Verilog to call. First, create a new project and create a demo.v top-level module. 1. Add IP cores 1. Click IP Catalog in Flow Navigator. 2. Select Multiplier under Math Functions, that is, multiplier, and double-click. 3. The parameter setting dialog box for the IP core will pop up. Click Documentation in the upper left corner to open the user manual of this IP core for reference. Here, directly set the input signals A and B to 4-bit unsigned data, and the others to default values, and click OK. 4. Click Generate in the window that pops up later. 2. Call IP core 1. Select IP Sources, expand and select mult_gen_0 - Instantiation Template - mult_gen_0.veo to open the instantiation template file. As shown in the figure, this code is the sample code for calling this IP core using Verilog. 2. Copy the sample code to the demo.v file and modify it. The final result is as follows. The code declares unsigned 4-bit variables a and b, assigning initial values of 7 and 8 respectively, which are used as multipliers; the unsigned 8-bit variable p is used to save the calculation result. clk is a clock signal with a period of 20ns written by Testbench; the mult_gen_0 mul(...) statement instantiates the module object mul of type mult_gen_0, and passes clk, a, b, and p as parameters. 3. Behavioral simulation verification Take demo as the top-level module, start behavioral simulation, and the waveform can be output. Set a, b, and p to display as unsigned decimal (right-click and select Radix - Unsigned Decimal). As shown in the figure, we can see that a=7, b=8, and p = a * b = 56 after the first clock rising edge. Calling IP core in block diagram (Block Design) Here is a simple example. By calling the multiplier IP core, a new module that can calculate square is generated. 1. Create a block diagram design file 1. Select Create Block Design in Flow Navigator to create a block diagram design file. 2. Enter the file name and click OK. 2. Add IP core 1. Right-click in the blank area of the block diagram and select Add IP. 2. You can directly search for the required IP core and double-click to confirm. 3. The IP core can be added and can be connected to other devices with wires. 4. Double-click the IP core symbol to open the parameter setting dialog box. Click Documentation in the upper left corner to view the manual of the IP core. Here, set the input A and B to 4 for unsigned type, and the others to the default value, and click OK to confirm. 3. Draw the circuit 1. Right-click in the blank area of the Diagram window and select Create Port. 2. In the pop-up window, set port a to a 4-bit input signal and click OK. 3. Connect a to both A and B. 4. In the same way, add an 8-bit output port p and connect it to P. 5. Add a clk clock input port and connect it to CLK. 6. The final result is shown in the figure. IV. Simulation Test 1. Right-click the block diagram design file design_1 and select Create HDL Wrapper. 2. Select the second option and click OK. 3. Open the generated design_1_wrapper.v file as shown in the figure. The code in the red box is used to call the Block Design module drawn earlier. 4. In the design_1_wrapper.v file, add the Testbench code to perform behavioral simulation. Modify the code as follows, assign the initial value of 8 to the input signal a, and connect clk to the clock signal c generated by the Testbench. 5. In the Simulation Sources folder, set design_1_wrapper.v as the top-level file of the behavioral simulation (right-click and select Set as Top). Start the behavioral simulation, and the final output waveform is as follows. It can be seen that after the first rising edge of clk, p = a*a = 64, which means that the square operation is implemented.

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