【Using IP core to realize D/A conversion in measurement and control system】

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【Using IP core to realize D/A conversion in measurement and control system】 [Copy link]

Abstract: Digital technology is used to realize D/A conversion in the measurement and control system with IP core, and it is implemented in a programmable logic device. It is not affected by temperature, can maintain high resolution, reduce the requirements for circuit accuracy and stability, and reduce the number of components.

In various electronic systems, digital circuits account for an increasing proportion. This is mainly because digital circuits have some outstanding advantages over analog circuits, such as:

*The active devices in digital circuits work in the saturation region and the cut-off region, and the working state is stable;

*Digital circuits process binary signals, which are easy to store and regenerate;

*Digital circuits are composed of a large number of identical basic units, such as gates and triggers, which makes them easy to integrate on a large scale and to use automated design tools.

Due to the above characteristics of digital circuits, coupled with the rapid development of digital computers and digital signal processing technology, digital circuits have greatly surpassed analog circuits in terms of integration scale, application scope and degree of design automation. More and more functions implemented by analog circuits are realized by digital circuits, and we have entered the era of digitalization of electronic systems.

Digital technology is used in the measurement and control system to realize the D/A originally realized by analog circuits by digital circuits.
1 Introduction to IP core

IP (Intellectual Property) cores design some commonly used but relatively complex functional blocks in digital circuits, such as FIR filters, SDRAM controllers, PCI interfaces, etc., into modules with modifiable parameters. Reusing IP cores is the main strategy for designers to win rapid time to market. As the scale of CPLD/FPGA becomes larger and larger, the design becomes more and more complex (the complexity of IC increases at a rate of 55% per year, while the design capability only increases by 21% per year), the main task of designers is to complete complex designs within the specified time period. Calling IP cores can avoid duplication of work and greatly reduce the burden on engineers, so the use of IP cores is a development trend.

IP cores include hard IP and soft IP. Configurable IP is parameterized and retargetable IP, which has the advantage of being able to tailor functionality to suit specific applications. These parameters include bus width, memory capacity, and enabling or disabling functional blocks.

The biggest advantage of hard IP is that it ensures performance, such as speed, power consumption, etc. However, hard IP is difficult to transfer to new processes or integrate into new structures and is not reconfigurable.

Soft IP is delivered in a comprehensive form, so it must be implemented in the target process and verified by the system designer. Its advantage is that the source code is flexible and can be re-targeted to multiple manufacturing processes and reconfigured in new functional levels.

However, most libraries are currently charged, but you can also download some free IP cores from the Internet.

2 Functions and features of D/A converters implemented using IP cores

Digital-to-analog converters (DACs) convert a binary number into a corresponding voltage value. Currently, commonly used D/A converters are composed of a resistor or capacitor weighted network, a switch controlled by a code element, and a reference voltage or current source. When the signal that the D/A converter needs to convert has a long word length per sampling, the accuracy requirements of these circuits are very high, and the circuit parameters must also be kept stable over the entire temperature range and throughout the service life. For example, a 16-bit D/A converter must have an MSB accuracy within 1/2 16, which is very difficult. Therefore, it is necessary to find a method to maintain high resolution while reducing the requirements for circuit accuracy and stability.

The synthesizable Delta-Sigma DAC (the term Delta-Sigma refers to arithmetic difference and sum, namely Δ- ∑ DAC) is a free IP core provided by Xilinx and can be downloaded from the Internet.

Delta-Sigma DAC uses digital technology, so it is not affected by temperature and can be implemented in a programmable logic device. Avoiding the use of matching resistors in D/A converters is not only cheaper, but also its conversion is linear. Delta-Sigma DAC is actually a high-speed single-bit DAC that uses digital feedback technology to generate a series of pulses at the output. The time portion of the signal in the pulse train that is high is proportional to the binary input, and an analog output signal is obtained when this pulse train passes through an analog low-pass filter.

Figure 1 is a top-level circuit diagram of a typical DAC implemented in a programmable logic device. The input signals include a reset signal, a clock signal, and a binary data bus. The output DACoutDrvr drives an external low-pass filter Vout from 0V to Vcco. Here Vcco is the power supply voltage of the FPGA I/O block. The detailed description of the input/output is listed in Table 1.

Table 1 Input and output description table

Signal	direction	describe
DACOUT	Output	Pulse train driving an external low-pass filter (via an output driver)
DACIN	enter	Digital input bus, the value must be set to the positive edge of the clock
clk	enter	Positive edge valid
Reset	enter	The reset signal initializes the SigmaLatch and the output D flip-flop

The binary input of DAC is an unsigned number. "0" represents the lowest voltage, and the output analog voltage is only positive. "0" input produces 0V output, and if all inputs are "1", the output will approximately reach Vcco.

Figure 2 is a block diagram of a Delta-Sigma DAC with a variable bit width binary input. For simplicity, the schematic depicts an 8-bit binary input DAC.

In this device, binary adders are used to generate both sums and differences. Although the input to the Delta Adder is unsigned, the outputs of both adders are signed. The Delta Adder calculates the difference between the DAC input and the current DAC output and represents it as a binary number. Since the output of the DAC is a single bit, it is either 1 or 0. As shown in Figure 2, the difference is generated when the input is added to the 10-bit number consisting of two copies of the Sigma Latch output and 0, which also compensates for the fact that DACIN is unsigned. The Sigma Adder adds its original output (stored in the Sigma Latch) to the current Delta Adder output.

The relationship between the output voltage and the input voltage in Figure 1 is:

VOUT = (DACIN/(2MSBI+1)) × VCCO

The unit in the formula is V.

For example, for an 8-bit DAC (MSBI = 7), the final output is as follows: when the DACIN input is 0, the output is also 0; when the DACIN input is the hexadecimal number FF, the output value is the maximum (255/256) × Vcco.

RC low-pass filters are suitable for most applications, and a simple RC low-pass filter works well.

Vs is defined as the absolute value of the change at Vout when the DAC input increases or decreases. For an 8-bit DAC, Vs is equal to (1/256) × Vcco.

Vout can generate a variable voltage between 0V and Vcco, and the specific value is determined by the bit width of DACIN and the input value.

Delta-Sigma DACs are suitable for low-frequency applications that require relatively high accuracy. In such applications, the voltage does not change very quickly, so the RC time constant can be large to reduce noise.

The most common application of this type of DAC is to generate normal DC voltages. This includes voltage-controlled oscillators, voltage-controlled operational amplifiers, I/O parameter voltages, programmable voltage sources, waveform generators (sine, triangle, etc.), reference voltages in A/D conversions, etc.

The Delta-Sigma DAC is an example of how high-speed programmable logic devices can be used in mixed-signal systems to reduce the number of components. The speed and density of programmable logic devices make them ideal for analog signal generation and processing.

library ieee;

use ieeestd_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity dac_ds is

port(reset :in std_logic;

clk :in std_logic;

din :in std_logic_vector(7 downto 0);--Signed integer

dout :out std_logic;

);

end dac_ds;

architecture arch_dac_ds of dac_ds is

signal error :std_logic_vector(9 downto 0);--Error accumulator is 2 bits larger

constant zeros:std_logic_vector(7 downto 0):=(others=>'0');

begin

process(reset,clk,din)

variable val :std_logic_vector(9 downto 0);

begin

if reset='1'then

error<=(others=>'0');

dout<='0';

elsif clk'event and clk='1' then

--val:=din+error;din is sign extended to nbits+2

val:=(din(din'high)&din(din'high)&din)+error;

if val(val'high)='0'then

dout<='1';

error<=val+("11"& zeros);

else

dout<='0';

error<=val+("01"&zeros);

end if;

end if;

end process;

end arch_dac_ds;

4 Chip selection and configuration

Select the MAX7000S series programmable logic device, and after compilation, the MAX+PLUS II software will automatically configure it into the EMP7032SLC44 chip, and program the device through the programming cable using the generated target file.

The D/A converter implemented by this IP core is used in a new intelligent resistance furnace temperature controller. Because the signal for adjusting the furnace temperature does not require fast changes, the input binary signal of the DAC is a slow-changing signal. For this low-frequency application, the RC time constant can be made larger to reduce noise. In this way, the synthesizable VHDL language Delta-Sigma DAC module is configured into the EMP7032 chip, achieving the expected effect.