[RTT & Renesas ultra-low power MCU RA2L1 development board] Evaluation of DAC module introduction and test

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[RTT & Renesas ultra-low power MCU RA2L1 development board] Evaluation of DAC module introduction and test [Copy link]

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DAC module introduction

Refer to the chapter <<31. 12-Bit D/A Converter (DAC12)>> in <<Renesas RA2L1 Group User's Manual: Hardware>>

feature

• 12-bit op amp, 1 channel.
• Can be started by ELC control.
• ADC12 can control the DA conversion timing to reduce the interference between AD and DA. It can also control the DA inrush current generation time to reduce the impact on AD acquisition accuracy.

The DAC parameters are as follows

block diagram

Related Pins

AVCC0 and AVSS0 are connected to VCC_MCU 3.3V and GND through E4 and E7 respectively.

DA0 corresponds to P014

Located on pin 21 of J2

register

DADR0: conversion value, select high or low bit according to (DADPR.DPSEL left or right alignment.

DACR: Control Enable Conversion

DADPR: Select whether the value of DADR0 is left-aligned or right-aligned.

DAADSCR: Controls whether to start conversion of ADC and DA synchronously.

DAVREFCR: Select reference voltage.

To configure the corresponding bits of ASEL and PCR select the pin function.

Operation process

1. Enable module clock MSTPCRD.MSTPD20 b20 is set to 0, the default is 1 and the module clock is not enabled.
2. Configure P014PFS.ASEL to 1 to enable simulation mode

P014PFS.PMR is set to 0

P014PFS.PDR is set to 0 Input Note that it must be set to input and cannot be set to output.

P014PFS.PCR is set to 0, no pull-up or pull-down

Note that PFS register operation requires unlocking PWPR

3. Set the data format DADPR Set the reference voltage DAVREFCR Set whether to synchronize ADC, DAADSCR
4. Write value DADR0
5. Start conversion DACR

Directly operate on registers

\ra_cfg\fsp_cfg\bsp\bsp_mcu_family_cfg.h defines

#define BSP_MCU_GROUP_RA2L1 (1)

\ra\fsp\src\bsp\cmsis\Device\RENESAS\Include\renesas.h中

#elif BSP_MCU_GROUP_RA2L1

#include "R7FA2L1AB.h"

Included #include "R7FA2L1AB.h"

This header file defines the base address of each peripheral register

The DAC register group structure is R_DAC

#define R_DAC ((R_DAC_Type *) R_DAC_BASE)

So for direct register operations, just include renesas.h.

The code is as follows

void dac_init(void)

{

R_MSTP->MSTPCRD_b.MSTPD20 = 0;

R_PMISC->PWPR_b.B0WI = 0;

R_PMISC->PWPR_b.PFSWE = 1;

R_PFS->PORT[0].PIN[14].PmnPFS_b.ASEL = 1;

R_PFS->PORT[0].PIN[14].PmnPFS_b.PCR = 0;

R_PFS->PORT[0].PIN[14].PmnPFS_b.PMR = 0;

R_PFS->PORT[0].PIN[14].PmnPFS_b.PDR = 0;

R_PMISC->PWPR_b.PFSWE = 0;

R_PMISC->PWPR_b.B0WI = 1;

R_DAC->DADPR_b.DPSEL = 0;

R_DAC->DAADSCR_b.DAADST = 0;

R_DAC->DAVREFCR_b.REF = 1;

//R_DAC->DADR[0] = 0x00;

//R_DAC->DACR_b.DAOE0 = 1;

}

void dac_out(uint16_t val)

{

R_DAC->DADR[0] = val;

R_DAC->DACR_b.DAOE0 = 1;

}

test

dac_init();

while (1)

{

dac_out(0);

rt_thread_mdelay(5000);

dac_out(2048);

rt_thread_mdelay(5000);

dac_out(4095);

rt_thread_mdelay(5000);

}

The measured voltage values of three voltage levels are output respectively.

The reference voltage is 3.39, and it can be seen that the error is less than 2%, and the linearity is good. If calibration is performed, the accuracy will be higher.

DAC Value	Measured voltage value	Theoretical value	deviation
0	0.01	0
2048	1.67	1.695	1.47%
4095	3.34	3.39	1.47%

question

The DAC pin must be set as analog input without pull-up or pull-down.

Note that although it is a DAC output, it cannot be set as output but must be set as input.

Jacktang

The result shows that the reference voltage is 3.39, and the error is less than 2%, and the linearity is good.