Different routing layers, same STUB

yvonneGan · Published on 2019-10-22 15:28

Different routing layers, same STUB [Copy link]

Original article by Mr. Gaosu | Huang GangN

years of valuable experience tells us that when encountering via stubs, the best way is to route the components on the surface layer to the lower layer, and the components on the bottom layer to the upper layer, so that the stub can be minimized. However, is there a situation where you feel that no matter which layer you route the stub, you can't lower it very low?

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Yes, there is such an operation, and we have seen it quite often. Under the ideal device layout, we like to put the high-speed signal transceiver chips on the same side, either on the surface layer or on the bottom layer. The reason is very simple. In this way, when we drill from the surface layer pin to the inner layer routing, as long as we go to the lower layer (the device is placed on the surface layer, if it is placed on the bottom layer, it is the opposite), the two vias will be shorter via stubs, which is conducive to improving the signal transmission quality. And don't always mention back drilling. It can ensure quality while saving costs and processing flow. I believe no one will refuse this good thing, right?

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However, some high-speed signals cannot put both devices on the front side, which seems to make us not pay attention to these high-speed routing. Do you think that as long as we want to give priority to their transmission, we can easily put them all on the surface first, right? There are things that even a concubine cannot guarantee, let alone a PCB engineer? For example, one of the components is a pin with high-speed routing on both sides...

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In fact, such components do exist, and they are widely used. One of them is our protagonist today, the PCIE gold finger. In many of our PCIE daughter card designs, we will encounter it. Its package is a double-sided pad structure. We have recently come into contact with a lot of such PCIE signals, mainly used in the current hot field of artificial intelligence .

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Like the highlighted TX link in the above picture (how to divide it into TX or RX? Look at the capacitor) is on the bottom layer, and our main chip is placed on the surface layer, then our internal routing seems to be unable to achieve the effect of placing it on the same side no matter which layer it goes to. Whether it is placed on the upper layer or the lower layer, one of the vias will have a long stub. At this time, we can imagine that the mood of the PCB engineer is just as contradictory as the situation in the figure below...

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After the previous preparation, let's talk about the case that this article wants to describe. The signal is PCIE3.0 protocol (8Gbps), and the board thickness is 2.0mm. In the first version, in order to save costs, the customer asked us if we could not back-drill. Then Mr. High Speed did not ask customers to back-drill at every turn, because after verification, we believed that when the routing is routed to the lower layer, the stub with long vias is about 60mil, which is still within the acceptable range for 8Gbps signals. The customer also submitted the board with a skeptical mentality, but fortunately, it didn't take long. After the board was returned, the customer tested the PCIE ( inserting the subcard into the base for testing) and found that it was really OK, and there was no problem with the transmission.

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After everything was fine, the customer started the second version. There were some changes to other routings, but the PCIE schematic diagram was not changed. Originally, PCIE should be copied directly, but because the routing at the bottom needs to give way to higher-speed signals, it is impossible to continue routing at the bottom layer as in the previous version. At this time, the PCB engineer thought that there would be a long via stub anyway, and the impact should be the same, so the routing was placed on the upper layer symmetrical to the lower layer, so the link of the second version became like this (since the difference between the two will be compared later , it will be more convincing if we use the same link with different routing layers to compare).

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This is what I said before, whether it is at the top or the bottom, there will be a long via stub that cannot be avoided. In fact, at first glance, it feels like it should be the same, because there is still the influence of a long and a short via stub. Is this actually the case?

We simulated and compared the two situations, and their transmission losses have a very surprising conclusion, that is, they are really the same. As shown below: After repeated confirmation by the high-speed gentlemen. It is confirmed that there are really two curves, and they are really exactly the same. The red curve is covered by the green one...

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After thinking about it later, it is actually correct. For this kind of linear time-invariant system, in fact, they should be the same. I don't want to explain the theory too much. If you are interested in this term, you can search it. In short, from the final reception point of view, first of all, the time is the same, and then the order of the long stub and the short stub does not matter when the stub is the same. The energy is the same when it is transmitted to the receiving end through oscillation. So it seems that in this case

, it really doesn't matter whether it is on the upper or lower layer? Many times when you have a conclusion that you think is correct, you often need to withstand the criticism of many people. For example, a colleague suggested that we give them a transceiver model to see if the eye diagram is the same? Well, this idea is very good, because for many people, S parameters are far less intuitive than the waveform or eye diagram in the time domain, so after we added the transceiver model for simulation, we immediately overturned this conclusion...

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Suddenly I found that the original gap was so big, and the eye height was actually more than 50mV different. Both waveforms look good, but in the PCIE link, this is only the daughter card part. After the base board is plugged in, the receiving margin will definitely be very small, so this is already a big difference.

After being surprised, we looked back at the return loss of these two links and finally found the difference.

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From the perspective of return loss, the result of version 1 is indeed better than that of version 2. This is the reason for the difference in eye diagrams. Therefore, in this case where there will always be via stubs, our choice of routing layer will actually have a great impact. We can no longer follow the traditional method of simply relying on the lower layer or the upper layer. At this time, we must analyze the specific problem specifically.

syeshu

Learned ~ very rewarding

Different routing layers, same STUB [Copy link]

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