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Before introducing the functions of the GPIO port, it is necessary to first explain the structural block diagram of the M3, so that you can better understand the bus structure and the location of the GPIO. Cortex M3 structure block diagram [size =3] As can be seen from the figure, the GPIO ports are all connected to the APB bus, and the M3 has two AHB to APB bridges, and the GPIO is directly connected to the AHB matrix, which can reduce the contention between the CPU and the DMA controller and obtain higher performance. The APB bus bridge is configured as a write buffer, so that the CPU or DMA controller can directly operate the APB peripherals without waiting for the bus write operation to complete. M3 digital I/O function: High-speed GPIO port, whose registers are moved to the peripheral AHB bus, can be byte, half-word and word addressing. Bit-level set and clear registers allow a single instruction to set and clear any bit of a port. All GPIO port registers support M3 bit-band operations. The entire port value can be written with a single instruction. GPIO port registers can be accessed by the GPDMA controller, and DMA data operations can be performed to synchronize with DMA requests. Individual I/O port direction can be controlled. All I/O ports default to pull-up inputs after reset. (Why? Because the microcontroller is connected to many devices. If it is used as an output after reset, the controller level state is uncertain, which may cause the peripheral devices to act, resulting in adverse effects. Therefore, half of them are used as input states after reset.) M3 digital ports that can generate interrupts: Each pin of PORT0 and PORT2 ports can provide interrupt function; The interrupt on each port can be programmed to generate an interrupt on the rising edge, falling edge or edge; Edge detection is asynchronous, so it can operate in the absence of a clock (such as power-down mode). With this feature, there is no need for level-triggered interrupts; Power-down wake-up is possible; Registers provide software with pending rising edge interrupts, pending falling edge interrupts, and the entire pending GPIO interrupt; GPIO0 and GPIO2 interrupts share the same NVIC channel with external interrupt 3 events. : 2. GPIO port register description Cortex M3 pin register description: ![]() Pin Mode Select Register Bits PINMODEx | | | | Pin enable pull-up resistor | | | | | Pins have no internal pull-up or pull-down resistors | | Pins have pull-down resistors enabled |
Relay mode description: When the pin is at a logic high level, the repeater mode can enable the pull-up resistor; when the pin is at a logic low level, the repeater mode can enable the pull-down resistor, so that when the pin is configured as an input and there is no external driver, it can maintain the last known state. PINSELx: Function selection register. Used to set the function of the PORT pin. When each bit of PINSELx is 0, it is used as a GPIO port. FIOxDIR: GPIO port direction register, which controls the direction of each port pin individually and can be accessed as byte (8-bit), half-word (16-bit) and word (32-bit) data. FIOxMASK: Mask register. Any write or read operation is only valid when the corresponding bit of this register is "0". FIOxPIN: Pin value register. As long as the pin is not configured as ADC, all other methods can read the current actual state of the port from this bit. Note: If the FIOPIN register is read, bits masked by "1" in the FIOMASK register will always read 0, regardless of the state of the physical pin. FIOxSET: The state of the output pin. Writing 1 causes the corresponding port pin to generate a high level. Writing 0 has no effect. Reading this register returns the current contents of the port output register. Only bits that are 0 in FIOMASK, that is, non-masked bits, can be changed. FIOxCLR: Controls the state of the output pin. Writing 1 causes the corresponding port pin to generate a low level. Writing 0 has no effect. Only the bits that are 0 in FIOMASK, i.e., the non-masked bits, can be changed. 2.1 GPIO Port Direction Register FIOxDIR (FIO0DIR??FIO4DIR- 0x2009 C000??0x2009 C080) This register can be used to control the direction of the pin when it is configured as a GPIO function. It is not necessary to set the direction of each pin according to the pin function. Note: GPIO pins P0.29 and P0.30 are shared with the USB D+/- pins and have the same direction. If FP0DIR bit 29 or bit 30 is configured as zero in the FIO0DIR register, P0.29 and P0.30 are both inputs. If FP0DIR bit 29 and bit 30 are configured as 1, P0.29 and P0.30 are both outputs.sans-serif]High-speed GPIO port direction register bit description[color= #000] bit [/ td][td=114] | [ align=left]value | | [/td ][/tr] | [/td][td= 114]FP0DIR FP1DIR FP2DIR FP3DIR FP4DIR[/ align] | | Controlled The pin is the input pin and the controlled pin is the output pin |
[color= #000] Word and half-word operations Basically similar, but the direction can be controlled by 8-bit registers or 16-bit registers respectively. I will not explain it here. Please refer to "Introduction to Cortex-M3 LPC1700》. 2.2 GPIO port output settings Register FIOxSET (FIO0SET??FIO7SET - 0x2009 C018??0x2009 C098) When the pin is configured in output mode When GPIO is used, this register generates a high level output on the port pin. When "1" is written to some bits of this register, the corresponding pin generates a high level. Writing "0" has no effect. If a pin output is required If the FIOxSET bit is set to low or the second function, then writing a 1 to the corresponding bit of FIOxSET has no effect. Reading the FIOxSET register returns the value of the register, which is determined by the previous write operation to FIOxSET and FIOxCLR (or FIOxPIN mentioned above). It does not reflect any external environment on the I/O pin. The port pins are restricted by the corresponding bits of the FIOxMASK register. serif]High-speed GPIO port output setting register bit description[color=# 000] bit | | | | [align= right] Reset value | [align= center]31:0 (word length data) | FP0SET[/align ] FP1SET FP2SET FP3SET FP4SET | | The output of the controlled pin does not change the control The pin output is set to high level | |
2.3 GPIO port output clear register FIOxCLR (FIO0CLR??FIO07CLR - 0x2009 C01C??0x2009 C09C) When the pin is in output mode is configured as GPIO When set to 0, this register generates a low level output on the port pin. Writing "1" to certain bits will cause the corresponding pin to generate a low level and clear the corresponding bit of the FIOxSET register. Writing "0" has no effect. If the pin is configured as an input or other function, then writing FIOxCLR has no effect on the pin. Port pins accessed through the FIOxCLR register are restricted by the corresponding bits in the FIOxMASK register. =center]High-speed GPIO port output clear register bit description[/ color]bit | | | | [align= right] Reset value | [/td][td= 114]FP0CLR FP1CLR FP2CLR FP3CLR FP4CLR[/ align] | | The output of the controlled pin does not change the control The pin output is set to low level | |
2.4 GPIO port pin value register FIOxPIN (FIO0PIN??FIO7PIN- 0x2009 C014??0x2009 C094) This register provides the port Values of pins that can be configured to perform digital-only functions. This register will give the current logic value of the pin, regardless of whether the pin is configured as an input or output, or as a GPIO or as some other optional digital function. For example, a particular port pin may have selectable functions such as GPIO input, GPIO output, UART receive, and PWM output. The current logic state of the pin can be read from the FIOxPIN register. If the pin is configured as an analog function, the pin state cannot be read when the analog configuration is selected. Selecting the pin as an A/D input disconnects the pin. The digital part of the connection. In this case, the pin value read from the FIOxPIN register is invalid. Write FIOxPIN register, the value of the FIOxPIN register is saved to the port output register without using the FIOxSET and FIOxCLR registers to obtain the entire write value. Since this feature affects the entire port, care must be taken when implementing it in the application. The port pins accessed through the FIOxPIN registers are restricted by the corresponding bits in the FIOxMASK register. Only the pins masked with 0 in the mask register are compatible with the high-speed GPIO port pin values. The current contents of the registers are related to each other. High-Speed GPIO Port Pin Value Register Bit Description Bit | | | | | | FP0VAL FP1VAL FP2 VAL FP3VAL FP4VAL | | |
2.5 High-speed GPIO port mask register FIOxMASK (FIO0MASK??FIO7MASK - 0x2009 C010??0x2009 C090) sans-serif]This register is used to mask certain port pins. The masked pins will not be accessible by write access via the FIOxPIN, FIOxSET or FIOxCLR registers. The mask register will also filter the contents of the corresponding port when the FIOxPIN register is read. A bit in this register that is "0" enables access to the corresponding physical pin by read or write access. If a bit in this register is "1", the corresponding bit will not be changed by write access and will not be reflected in the updated FIOxPIN register when read. High-Speed GPIO Port Pin Value Register Bit Description bit | | [/td][td= 114] | | | FP0VAL FP1VAL FP2 VAL FP3VAL FP4VAL | | |
2.1 GPIO port direction register FIOxDIR (FIO0DIR??FIO4DIR- 0x2009 C000??0x2009 C080) Note: GPIO pins P0.29 and P0.30 are shared with the USB D+/- pins and have the same direction. If FP0DIR bit 29 or bit 30 is configured as zero in the FIO0DIR register, P0.29 and P0.30 are both inputs. If FP0DIR bit 29 and bit 30 are configured as 1, P0.29 and P0.30 are both outputs. High-speed GPIO port direction register bit description bit | | [/td][td= 114] | | | FP0DIR FP1DIR FP2 DIR FP3DIR FP4DIR | | The controlled pin is an input pinThe controlled pin is an output pin | |
The operation of word and half word is basically similar, except that the direction can be controlled by 8-bit register or 16-bit register respectively. I will not explain it here. Please refer to "Cortex-M3 LPC1700 in Simple Terms". 2.2 GPIO Port Output Setting Register FIOxSET (FIO0SET??FIO7SET - 0x2009 C018??0x2009 C098) When the pin is configured as GPIO in output mode, this register generates a high level output on the port pin. When writing "1" to certain bits of this register, the corresponding pin generates a high level. Writing "0" has no effect. If the pin is required to output a low level or a second function, then writing 1 to the corresponding bit of FIOxSET has no effect. Reading the FIOxSET register returns the value of the register, which is determined by the previous write operation to FIOxSET and FIOxCLR (or FIOxPIN mentioned above). It does not reflect any external environment on the I/O pin. The port pins accessed through the FIOxSET register are restricted by the corresponding bits of the FIOxMASK register. High-speed GPIO port output setting register bit description bit | | [/td][td= 114] | | | FP0SET[/align ] FP1SET FP2SET FP3SET FP4SET | | The output of the controlled pin does not change the control The pin output is set to high level | |
[ 2.3 GPIO port output clear register FIOxCLR (FIO0CLR??FIO07CLR - 0x2009 C01C??0x2009 C09C) This register generates a low level output on the port pin when the pin is configured as a GPIO in output mode. Writing a "1" to certain bits will cause the corresponding pin to Generates a low level and clears the corresponding bit in the FIOxSET register. Writing "0" has no effect. If the pin is configured as an input or other function, writing FIOxCLR has no effect on the pin. Port pins accessed through the FIOxCLR register are affected by Limits on the corresponding bits of the FIOxMASK register. High-speed GPIO port output clear register bit description [color=# 000] bit | | | | [align= right] Reset value | [/td][td= 114]FP0CLR FP1CLR FP2CLR FP3CLR FP4CLR[/ align] | | The output of the controlled pin does not change the control The pin output is set to low level | |
[ 2.4 GPIO port pin value register FIOxPIN (FIO0PIN??FIO7PIN- 0x2009 C014??0x2009 C094) This register provides the values of port pins that can be configured to perform digital-only functions. This register will give the current logic value of the pin, regardless of whether the pin is configured As input or output, or as GPIO or as other optional digital functions. [color=# 000000] For example, a particular port pin may have selectable functions such as GPIO input, GPIO output, UART receive, and PWM output. Regardless of the function that the pin is configured to, its current value can be read from the corresponding FIOxPIN register. logic state. If the pin is configured as an analog function, the pin state cannot be read when the analog configuration is selected. Selecting the pin as an A/D input disconnects the digital portion of the pin. In this case, the pin value read from the FIOxPIN register is invalid.sans-serif]When writing to the FIOxPIN register, the value of the FIOxPIN register is saved to the port output registers without using the FIOxSET and FIOxCLR registers to obtain the entire written value. Because this feature affects the entire port, care should be taken in the application. The port pins accessed through the FIOxPIN register are restricted by the corresponding bits of the FIOxMASK register. Only the pins masked with 0 in the mask register are correlated with the current contents of the high-speed GPIO port pin value register. High-Speed GPIO Port Pin Value Register Bit Description bit | | [/td][td= 114] | | | FP0VAL FP1VAL FP2 VAL FP3VAL FP4VAL | | |
2.5 High-speed GPIO port mask register FIOxMASK (FIO0MASK??FIO7MASK - 0x2009 C010??0x2009 C090) This register is used to mask certain port pins. The masked pins will not be accessible through the FIOxPIN, FIOxSET or FIOxCLR registers. The mask register will also filter the contents of the corresponding port when the FIOxPIN register is read. A bit in this register that is "0" enables access to the corresponding physical pin by read or write access. If a bit in this register is "1", the corresponding bit will not be changed by write access and will not be reflected in the updated FIOxPIN register when read. High-speed GPIO port pin value register bit description bit | | [/td][td= 31:0 (word length data) | FP0VAL[/align ] FP1VAL FP2VAL FP3VAL FP4VAL | | The output of the control pin is set to low The pin output of the level control is set to high level | |
For common [/ color]ARMprocessors, their GPIO ports can basically be configured as input mode, output mode, open drain or push-pull mode. Xin Tang's M0, all I/O are all in quasi-bi-end mode; for NXP Verdana, sans-serif]M3processor, GPIO can be configured as pull-up, pull-down, open-drain or neutral. Follow-up mode. Open-drain output and push The difference between the output: Push-pull output: The push-pull structure generally refers to two transistors being controlled by two complementary signals respectively, and one transistor is always turned on while the other is turned off. It can output high and low levels and connect digital devices. The normal pull-out/sink current is 4mA, and the short-time limit can reach 40mA, but not every pin can output so much. Open drain output: output The terminal is equivalent to the collector of the transistor. To get a high level state, a pull-up resistor is required. It is suitable for current-type driving and has a relatively strong ability to absorb current (generally within 20mA). Open-drain circuit concept The "drain" mentioned here refers to the drain of the MOS FET. Similarly, the "collector" in the open collector circuit refers to the collector of the transistor. An open-drain circuit is a circuit that uses the drain of a MOS FET as the output. The general usage is to add a pull-up resistor to the circuit outside the drain. A complete open-drain circuit should consist of an open-drain device and an open-drain pull-up resistor. /size] [size= 3] The circuit that forms the open-drain form has the following characteristics: 1. Utilize the driving capability of the external circuit to reduce the internal driving of the IC. When the internal MOSFET of the IC is turned on, the driving current flows from the external VCC through R pull-up , MOSFET to GND. Only a small gate drive current is needed inside the IC. As shown in Figure 1. 2. Multiple open-drain output pins can be connected to one line to form an "AND logic" relationship. As shown in the figure, when When any one of PIN_A, PIN_B, or PIN_C becomes low, the logic on the open-drain line is 0. This is also the principle of I2C, SMBus and other buses to determine the bus occupancy status. 3. The transmission level can be changed by changing the voltage of the pull-up power supply. The logic level of the IC is determined by the power supply Vcc1, and the output high level is determined by Vcc2. In this way, we can use low-level logic to control the output of high-level logic. 4. If the open-drain pin is not connected to an external pull-up resistor, it can only output a low level (therefore, for the P0 port of the classic 51 microcontroller, If you want to do input and output functions, you must add an external pull-up resistor, otherwise you cannot output high-level logic). #252525]![]() Question Collection 1. The characteristics of the quasi-bidirectional IO structure are: 1. The output structure is similar to the OC gate. When the output is low, the internal NMOS is turned on, and the driving capability is strong (800uA); the output high level relies on the internal pull-up resistor, and the driving capability is weak (60uA). 2 There is always an internal resistor to pull up, and the high-level output current capacity is very weak, so even if the IO port is short-circuited to the ground for a long time, the IO port will not be damaged (similarly, the IO port has a strong low-level output capacity, and it cannot be short-circuited to VCC for a long time when it is a low-level output) 3 When used as an input, because the OC gate has the "line and" characteristic, the IO port must be set to a high level (so the buttons are mostly connected to the common ground) 4 When used as an output, the output low level can drive the LED (also very weak), and the output high level usually requires an external buffer circuit (so the LED is mostly connected to the common anode) 5 It is more convenient to simulate the bus of the OC structure with software-----for example, the IIC bus* OC gate: the collector of the triode is called open circuit, and the drain of the field effect tube is called open circuit, which is referred to as open drain output. It has the ability of "line and", and 0 gets 0. * Why is it designed to be weak in high level and strong in low level when output--it is considering the popular TTL device input at that time. 2. The difference between different IO modes? Simply put: "quasi-bidirectional IO port" must be set to "1" with a write instruction before reading, and this step is not required for writing. "True bidirectional IO port" can be read and written directly. "Tri-state IO port" has high, low level, and high impedance states. I understand high impedance as: this pin is disconnected from the internal circuit.
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